Xilinx, Inc.

Marvell International Limited

Jds Uniphase Corporation

E20 Communications, Inc.

E2o Communications, Inc.

Kee Hian Tan

Yong Hwee Sim

Liew Chuang Chiu

Ron C Pang

Yohan Usthavia Frans

Siok Wei Lim

Nakul Narang

Yipeng Wang

Kun-Yung Chang

Tat T Ming

Ping-Chuan Chiang

Edwin Dair

Kok Lim Chan

Chin Yang Koay

Hongyuan Zhao

Tat Ming Teo

Kan Li

Hai Bing Zhao

Thart Fah Voo

Hsung Jai Im

Stanley Yuanshih Chen

Gourav Modi

Arianne Roldan

Haibing Zhao

Luhui Chen

A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

Transmit driver architecture with a jtag configuration mode, extended equalization range, and multiple power supply domains

A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter may filter the control signal. The second flipped voltage follower may generate the output voltage based on the filtered bias voltage and the filtered control signal.

Low-noise reference voltage generator

A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

On-die receiver coupling capacitance testing

Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

Clock phase aligner for high speed data serializers

A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

Quadrature clock correction circuit for transmitters

Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.

Thermal calibration of a ring modulator

A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.

Digital-to-analog converter (DAC)-based driver for optical modulators

A frequency divider circuit () includes a frequency sub-divider () to provide a frequency divided clock, a delay circuit () configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit () configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.

High speed frequency divider

A driver circuit includes a driver array configured to generate, at a first output, a multi-bit output signal including a first bit associated with a predetermined first-bit amplitude and a second bit associated with a predetermined second-bit amplitude. The driver array includes first-bit driver slices coupled in parallel between a first input of first data associated with the first bit and the first output, and second-bit driver slices coupled in parallel between a second input of second data associated with the second bit and the first output. A first ratio between a first number of enabled first-bit driver slices and a second number of enabled second-bit driver slices is different from a second ratio between the predetermined first-bit amplitude and the predetermined second-bit amplitude.

Method and system for generating a modulated signal in a transmitter

Apparatus and associated methods relate to a programmable resistor having a resistance iteratively programmed by a calibration control loop. In an illustrative example, the calibration control loop may alternately sample the programmable resistance and a reference resistance by producing a corresponding voltage drop across the resistors. The voltage drops may, for example, be induced by the same constant current source. The calibration control loop may compare the voltage drops with a comparator, for example. In some examples, the comparator may provide a count direction signal to a logic block, generating a calibration code. The calibration code may, for example, be applied to the programmable resistor, such that the resistance of the programmable resistor iteratively approaches the resistance of the reference resistor. Various programmable resistors within a calibration control loop may, for example, substantially improve termination impedances of high-speed transmission lines and may mitigate random resistive mismatch variations.

Global resistor calibration for transceivers

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

Impedance and swing control for voltage-mode driver

An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.

Data-dependent current compensation in a voltage-mode driver

An example voltage regulator includes an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node. The voltage regulator further includes a first transistor that includes a source coupled to the output node, and a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node. The voltage regulator further includes a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor. The voltage regulator further includes an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor.

Fast transient low drop-out voltage regulator for a voltage-mode driver

An apparatus includes a decision feedback equalizer configured to receive a parallel signal generated based on a first clock. The decision feedback equalizer includes a first equalization block configured to receive a first symbol of a first set of parallel symbols provided by the parallel signal during a first clock cycle of the first clock. A decision feedback equalization is performed by the first equalization block to the first symbol to provide a first decision to a second equalization block. The second equalization block is configured to receive a second symbol of the first set of parallel symbols and perform a decision feedback equalization to the second symbol using the first decision received from the first equalization block to provide a second decision during the first clock cycle.

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Singapore, Singapore

Kee Hian Tan