Metisx Co., Ltd.

Kee Bum Shin

Do Hun Kim

Kwang Sun Lee

Ju Hyun Kim

A method for processing multiple transactions converted from a single transaction is provided, which is performed by a processor including at least one core and includes converting a first transaction conforming to an instruction according to an instruction set architecture (ISA) into a plurality of second transactions conforming to the register size of the core, and transferring, by the load-store unit (LSU) of the core, the plurality of second transactions to the cache, in which the LSU may be configured to further transfer, to the cache, conversion information indicating whether the plurality of second transactions are converted from the first transaction.

Method for processing multiple transactions converted from single transaction in processor, and processor for performing same

The present disclosure relates to a manycore system which includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each of the plurality of clusters includes a program memory configured to store a program associated with the job requested to be offloaded, a plurality of cores configured to execute one or more threads associated with the job, and a management module configured to allocate one or more tasks associated with the job to the plurality of cores based on job loads of the plurality of cores, and control thread execution corresponding to the one or more allocated tasks. Each core includes thread areas configured to independently store and track an execution state of each thread executed on the core, and each thread executed on the core is independently executed using a separate thread area.

Manycore system

A multi-threading processor is provided, which includes a cache including a memory and a controller, and a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads, in which the core is configured to determine an occurrence of a data hazard for the plurality of threads and stall operations of the plurality of threads, receive, from the cache, hint information instructing a first thread of the plurality of threads to operate, and initiate an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained.

Multi-threading processor and operating method thereof

A method for processing multiple transactions converted from a single transaction related to each of a plurality of threads is provided, in which the method is performed by a processor including at least one core and includes converting a first transaction related to at least one of the plurality of threads into a plurality of second transactions, transferring, by a load-store unit (LSU) of the core, the plurality of second transactions to a subordinate or a cache, receiving, by the LSU, a plurality of data units related to the second transactions from the subordinate or the cache, and merging, by the LSU, the plurality of data units, in which the LSU is configured to further transfer interleaving deactivation information that causes the subordinate or the cache to deactivate interleaving.

A multiprocessor system includes a plurality of processors, a first cache device corresponding to a first processor of the plurality of processors and including a first cache memory configured to store a plurality of first cache lines, and a second cache device at different level than the first cache device, corresponding to the plurality of processors, and including a second cache memory that stores a plurality of second cache lines, in which the first cache device is configured to, in response to a request related to data access, search the first cache memory for data, and the second cache device is configured to, in response to the data cache-missed in the first cache memory, search the second cache memory for data, and in response to the data cache-hit in the second cache memory, set cache line of the second cache memory corresponding to the data as clean cache line.

Growing community of inventors

Yongin-si, South Korea

Kee Bum Shin