Shenzhen Microbt Electronics Technology Co., Ltd.

Ke Xue

Zuoxing Yang

Chao Xu

Zhijun Fan

Nan Li

Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Circuits and methods for performing hash algorithm

The present disclosure relates to a circuit for performing a hash algorithm, computing chip, data processing device and method. A circuit includes: operation stages in a pipeline structure each including 0th to 15th expansion registers; expansion data operation logic modules each disposed between two adjacent operation stages including a first operation stage and its subsequent second operation stage, and including a first sub-module configured to compute data in a 0th expansion register of the second operation stage based on data in a 1st expansion register of the first operation stage and a second sub-module configured to compute data in a 15th expansion register of the second operation stage based on data in a 0th expansion register of the first operation stage: data in an (i&#x2212;1)th expansion register of the second operation stage is data in an ith expansion register of the first operation stage.

Circuit for performing hash algorithm, computing chip, data processing device and method

This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Computing chip, hashrate board and data processing apparatus

This disclosure relates to a device performing hash algorithm. A hash engine includes an operation module performing a hash operation on a data block and a clock module. The operation module includes operation stages each including registers and a combinational logic module. A digital signal based on the data block is sequentially delivered along the operation stages. Outputs of a first set of registers are coupled to an input of the combinational logic module of the current operation stage. Inputs of a second set of registers are coupled to an output of a combinational logic module of a previous operation stage. A clock signal, provided by the clock module to each operation stage, is sequentially delivered along a multi-stage clock driving circuits of the clock module. For the first and second sets of registers, a delivery direction of the digital signal is the same as that of the clock signal.

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Guangdong, China

Ke Xue