Pericom Semiconductor Corporation

Sony Computer Entertainment Inc.

Ke Wu

David Kwong

Michael Yimin Zhang

Tony Yeung

Eric Hsuming Chen

Arnold Chow

Lost frame reconstruction is described. A previous good or reconstructed frame may be analyzed to determine a category for the lost frame. A percentage Pmay be associated with the determined category of the lost frame. A top Ppercent magnitude samples may be zeroed out in an excitation of the previous good or reconstructed frame to produce a reconstruction excitation. The reconstruction excitation may be applied to one or more linear prediction coefficients for the previous good or reconstructed frame to generate a reconstructed frame.

Low complexity no delay reconstruction of missing packets for LPC decoder

A frequency-multiplying circuit generates a multiple of the fundamental frequency of a crystal that oscillates. A first differential multiplier is coupled to the crystal nodes and generates a frequency-doubled output. The frequency-doubled output is applied to an op amp that buffers the output and compares it to a reference to generate a pair of differential buffered signals. The differential buffered signals are applied to a second differential multiplier that generates a final quadrupled-frequency output. The differential multipliers can each have a pair of differential transistors that receive signals that oscillate out-of-phase to each other by 180 degrees. The drains of the differential transistors connect together at a summing node to sum the transistor currents, producing the frequency-doubled output. A crystal driver circuit using cross-coupled and direct-coupled transistors may also be attached to the crystal nodes.

4X crystal frequency multiplier with op amp buffer between 2X multiplier stages

A self-biasing differential buffer generates a self-bias voltage from its inputs. A first amplifier receives a first input signal on gates of four transistors&#x2014;p and n-channel drive transistors in a drive branch and p and n-channel bias-generating transistors in a bias-generating branch. Current source and current sink transistors source and sink current to both branches. The drains of the drive transistors drive a differential output, while the drains of the bias-generating transistors drive through a transmission gate to a self-bias node. The second amplifier receives the second input signal and has the same structure, with one branch driving the self-bias voltage through another transmission gate, and another branch driving a complementary differential output. The bias-generating branches use smaller transistors so that only a small current is used to generate the self-bias voltage. The self-bias node is fed to the gates of current source and sink transistors.

Self-biasing differential buffer with transmission-gate bias generator

A register chip for double-data-rate (DDR) memory modules operates in 1:1 mode or 1:2 mode. A differential input clock is buffered to generate a slave clock that continuously clocks slave stages of flip-flops, and gated to generate a first clock pulsing only in 1:1 mode and a second clock pulsing only in 1:2 mode. The master stage has two input transmission gates, one activated by the first clock and another activated by the second clock. In 1:1 mode a first data bit is sampled by the first clock, but in 1:2 mode a second data bit is sampled by the second clock. The sampled bit is inverted and applied to the slave stage and to a feedback gate that has transistors gated by the first and second clocks. The clock-to-output delay is improved since an output mux is replaced by the muxing function built into the master stage.

Muxed-output double-date-rate-2 (DDR2) register with fast propagation delay

A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.

Data register for buffering double-data-rate DRAMs with reduced data-input-path power consumption

A differential output buffer has a primary stage and a secondary stage that each directly drive differential outputs. Link transistors between the secondary stage and the differential outputs are eliminated. The primary stage continuously receives differential inputs applied to gates of n-channel sourcing and sinking transistors. The sources of the sourcing transistors and the drains of the sinking transistors are connected to the true and complement differential outputs. The secondary stage also has n-channel sourcing and sinking transistors directly connected to the differential outputs. Pulsed inputs applied to secondary-stage gates are normally low, disabling the sourcing and sinking transistors in the secondary stage to disable the secondary stage. However, during a switching transient, the pulsed inputs are pulsed on, allowing the secondary stage to drive a boost current to the differential outputs. This boost current sharpens rise and fall edges to compensate parasitic capacitances, opening the eye pattern.

Low-voltage differential driver with opened eye pattern

An electro-static-discharge (ESD) protection circuit is coupled between power and ground. It protects core circuits in a semiconductor chip. The ESD protection circuit is an active circuit that drives the gate of an n-channel clamp transistor. The clamp transistor shunts current from power to ground when its gate is driven high during an ESD event. A voltage divider generates a sense voltage that drives a first inverter. The sense voltage is normally much lower than the switch threshold of the first inverter. When an ESD voltage spike occurs, the sense voltage rises above the switch threshold, switching the output of the first inverter. A string of inverters is driven by the first inverter, with a final inverter driving the gate of the clamp transistor. An extending n-channel transistor drives the input of the final inverter low when the clamping transistor is on, extending the discharge time. A hysteresis p-channel transistor drives the output of the first inverter high, delaying turn-on of the clamp transistor. This increases the voltage required to trigger the protection circuit.

Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

A fail-safe circuit for a pair of differential input lines detects when one or both lines are open. Each line has a pull-up of a switched p-channel transistor in series with a resistor or another p-channel transistor that has its effective resistance controlled by a gate bias. The gate of the switched p-channel transistor is driven to ground when power is applied to the gate of a grounding n-channel transistor. When power is off, a p-channel connecting transistor charges the gate node from the differential input line when a positive voltage is applied to the input line, such as during a leakage test. Charging the gate node prevents the switched p-channel transistor from turning on, blocking a leakage current path through the pull-up. An N-well bias circuit can be added, which connects the N-well under p-channel transistors to power or the gate node or the input line.

Fail-safe circuit with low input impedance using active-transistor differential-line terminators

A power-up-reset circuit draws zero standby current. Rather than use a voltage divider that always draws current, a capacitive-pullup divider is used as the first stage. The capacitive-pullup divider has a capacitor to power (Vcc) and n-channel series transistors to ground. A sensing node between the capacitor and n-channel series transistors is initially pulled high to Vcc as Vcc is ramped up. The n-channel transistors remain off until Vcc reaches about 1.5 volts. Then the n-channel transistors pull the sensing node quickly to ground, ending the reset pulse. The second stage has a capacitor to ground that initially holds a threshold node low. A p-channel transistor has a gate connected to the sensing node and charges up the capacitor when the sensing node falls to ground. A third stage is triggered to change state as the capacitor is charged up by the p-channel transistor. Then a Schmidt trigger toggles, as do downstream inverter stages. A feedback signal goes low, disabling the gate of a pulldown n-channel transistor in the second stage. This disables a power-to-ground current path.

Zero standby-current power-on reset circuit with Schmidt trigger sensing

A differential amplifier has a wide common-mode input range since it uses two complementary amplifiers. One amplifier has a differential pair of n-channel transistors while the other amplifier has a differential pair of p-channel transistors. The input range is extended further by replacing the current mirror transistors with load resistors. The load resistors continue to supply current to the differential pair transistors even when the input is within a transistor-threshold of the power or ground rails. The current through the load resistors is mirrored to intermediate mirror transistors that have their gate connected to the resistor's terminal node. Current in the differential amplifiers is mirrored as if current-mirror transistors were present rather than the load transistors. The intermediate mirror transistors supply current to inverse-mirror transistors. Since the inverse mirror transistors are of the opposite type as the intermediate mirror transistors, the inverse mirror transistors continue to operate when the input voltage is in the extreme of the range that shuts off the intermediate mirror transistors. Outputs of the intermediate and inverse mirror transistors of the two amplifiers are connected together and buffered by a final stage.

Complementary differential amplifier with resistive loads for wide common-mode input range

A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor. The sources and drains of the compensating transistors are connected together so that they transistors act as capacitors. A connecting p-channel transistor is added in parallel with the main p-channel transistor. The connecting p-channel transistors is turned on early, before the main p-channel transistor, to increase the capacitance by connecting the two network nodes. The increased capacitance decreases the voltage spike caused by a fixed amount of injected charge.

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San Jose, CA, United States of America

Ke Wu