University of Virginia Patent Foundation

Acumino

Ke Wang

Kevin Skadron

Mircea R Stan

Elaheh Sadredini

Runjie Zhang

Minas Liarokapis

Patrick McKinley Jarvis

Gholamreza Rahimi

Jayden Chapman

Che-Ming Chang

Brett Meyer

A hardware accelerated solution of the SPM (Sequential Pattern Mining) is proposed using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs) The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. The multi puss pruning strategy of the GSP is implemented is the APs fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90× and 29× speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU (Central Processing Unit) and GPU (Graphics Processing Unit) GSP implementations, respectively. The proposed CPU-AP solution also outperforms the state-of-the-art PrefixSpan and SPADE (Sequential PAttern Discovery using Equivalence classes algorithms on multicore CPU by up to 452× and 49× speedups.

Sequential pattern mining with the micron automata processor

A method for training and/or testing a robot control module. The method includes generating an instruction specified by a robot control module configured for robot training and/or testing, the instruction indicating how a human-driven robot task is to be performed when training and/or testing the robot control module; providing the instruction to a mixed reality device worn by a human data collector, the mixed device rendering the instruction in a manner that shows the human data collector how to perform the human-driven robot task; collecting performance data and environmental data in response to the human data collector attempting to perform the human-driven robot task using the data collection device; receiving feedback data in response to the human data collector attempting to perform the human-driven robot task specified by the instruction; and updating the robot control module using the feedback data and the collected performance and environmental data.

System for testing and training robot control

A data collection system that performs data collection of human-driven robot actions for robot learning. The data collection system includes: i) a wearable computation subsystem that is worn by a human data collector and that controls the data collection process and ii) a human-machine operation interface subsystem that allows the human data collector to use the human-machine operation interface to operate an attached robotic gripper to perform one or more actions. A user interface subsystem receives instructions from the wearable computation subsystem that direct the human data collector to perform the one or more actions using the human-machine operation interface subsystem. A visual sensing subsystem includes one or more cameras that collect raw visual data related to the pose and movement of the robotic gripper while performing the one or more actions. A data collection subsystem receives collected data related to the one or more actions.

Wearable robot data collection system with human-machine operation interface

Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

System for placement optimization of chip design for transient noise control and related methods thereof

A method of searching tree-structured data can be provided by identifying all labels associated with nodes in a plurality of trees including the tree-structured data, determining which of the labels is included in a percentage of the plurality of trees that exceeds a frequent threshold value to provide frequent labels, defining frequent candidate sub-trees for searching within the plurality of trees using combinations of only the frequent labels, and then searching for the frequent candidate sub-trees in the plurality of trees including the tree-structured data using a plurality of pruning kernels instantiated on a non-deterministic finite state machine to provide a less than exact count of the frequent candidate sub-trees in the plurality of trees.

Methods, circuits, and articles of manufacture for frequent sub-tree mining using non-deterministic finite state machines

A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile 'positive charged particles' and current resources as a 'negative charged back-ground.' The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.

System, method, and computer readable medium for walking pads: fast power- supply pad-placement optimization

The present invention introduces the development of a flexible CPU-AP (Computer Processing Unit-Automata Processor) computing infrastructure for mining hierarchical patterns based on Apriori algorithm. A novel automaton design strategy, called linear design, is described to generate automata for matching and counting hierarchical patterns and apply it on SPM (Sequential Pattern Mining). In addition, another novel automaton design strategy, called reduction design, is described for the disjunctive rule matching (DRM) and counting. The present invention shows performance improvement of AP SPM and DRM solutions and broader capability over multicore and GPU (Graphics Processing Unit) implementations of GSP SPM, and shows that AP SPM and DRM solutions outperform state-of-the-art SPM algorithms SPADE and PrefixSpan (especially for larger datasets).

Disjunctive rule mining with finite automaton hardware

The present invention discloses a heterogeneous computation framework, of Association. Rule Mining (ARM) using Micron's Autotmata Processor (AP). This framework is based on the Apriori algorithm. Two Automaton designs are proposed to match and count the individual itemset. Several performance improvement strategies are proposed including minimizing the number of reporting vectors and reduce reconfiguration delays. The experiment results show up to 94&#xd7; speed ups of the proposed AP-accelerated Apriori on six synthetic and real-world datasets, when compared with the Apriori single-core CPU implementation. The proposed AP-accelerated Apriori solution also outperforms the state-of-the-art multicore and GPU implementations of Equivalence Class Transformation (Eclat) algorithm on big datasets.

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Charlottesville, VA, United States of America

Ke Wang