Intel Corporation

Ke Sun

Rodrigo Branco

Kekai Hu

Henrique Kawakami

Siddhartha Chhabra

Prashant Dewan

Junhai Qiu

Henrique De Medeiros Kawakami

An embodiment of an integrated circuit may comprise a branch predictor to predict whether a conditional branch is taken for one or more instructions, the branch predictor including circuitry to identify a loop branch instruction in the one or more instructions, and provide a branch prediction for the loop branch instruction based on a context of the loop branch instruction. Other embodiments are disclosed and claimed.

Context-based loop branch prediction

Methods and apparatus relating to Organic Light Emitting Diode (OLED) compensation based on protected content are described. In an embodiment, secure memory stores data that is only accessible by trusted logic. Display controller logic circuitry updates pixel values to be stored in the secure memory based on a plurality of frames. The display controller logic circuitry allows access by untrusted software to the updated pixel values after a first number of updates to the pixel values stored in the secure memory. Other embodiments are also disclosed and claimed.

Organic light emitting diode (OLED) compensation based on protected content

The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side-channel based attack, such as one or more classes of an attack commonly known as Spectre. Novel instruction prefixes, and in certain embodiments one or more corresponding instruction prefix parameters, may be provided to enforce a serialized order of execution for particular instructions without serializing an entire instruction flow, thereby improving performance and mitigation reliability over existing solutions. In addition, improved mitigation of such attacks is provided by randomizing both the execution branch history as well as the source address of each vulnerable indirect branch, thereby eliminating the conditions required for such attacks.

Efficient mitigation of side-channel based attacks against speculative execution processing architectures

In one embodiment, a processor comprises a decoder to decode a first instruction, the first instruction comprising an opcode and at least one parameter, the opcode to identify the first instruction as an instruction associated with an indirect branch, the at least one parameter indicative of whether the indirect branch is allowed; and circuitry to generate an error message based on the at least one parameter.

Fine grained control flow enforcement to mitigate malicious call/jump oriented programming

The present disclosure is directed to systems and methods of selectively implementing SCA mitigation elements on a per-thread basis to mitigate the effects of side channel attacks. Processor core circuits initiate a plurality of processor threads. Each of a plurality of SCA mitigation features include one or more SCA mitigation elements. SCA mitigation control circuitry associates a register circuit with each respective one of the plurality of processor threads initiated by the processor core circuits. The SCA mitigation control circuitry selectively ENABLES/DISABLES one or more SCA mitigation elements for each of the plurality of processor threads. The ENABLEMENT/DISABLEMENT of each of the SCA mitigation elements may be autonomously adjusted by the SCA mitigation control circuitry and/or manually adjusted via one or more user inputs provided to the SCA mitigation control circuitry.

Per thread side channel attack protection

A computing apparatus, including: a processor; a memory; and encoded logic to instruct the processor to: identify within the memory a payload that is suspected to be a return-oriented programming (ROP) chain; execute the suspected ROP chain in a speculative execution path within the processor; force a missed prediction of the speculative execution path; determine that the suspected ROP chain executed through; and take a security action responsive to the determining.

Mitigation of return-oriented programming exploits

Various systems and methods for memory management are described herein. A system for managing memory includes a memory management unit to: receive an indication of a memory allocation request; identify a memory region to satisfy the memory allocation request; determine whether the memory region has a tracking record in a tracking data structure, the tracking data structure configured to track whether a particular memory region has any references pointing to it; and revise the tracking record in the tracking data structure when the memory region has the tracking record.

Growing community of inventors

Portland, OR, United States of America

Ke Sun