Yangtze Memory Technologies Co., Ltd.

Ke Liang

Chunyuan Hou

Zhipeng Dong

Liang Qiao

Li Xiang

Qiang Tang

Chun Yuan Hou

Hongtao Liu

Ying Huang

Fan Yang

Yueping Li

Ling Chu

Weiwei He

Manxi Wang

Dejun Li

Ning Zhang

Yi Cao

Guangyu Bai

Examples of the present disclosure provide a memory device and an operation method thereof, and a memory system. The memory device includes: a memory cell array including memory cells, wherein the memory cells are divided into memory planes; bit lines; page buffer circuits, wherein each of the page buffer circuits includes page buffer groups, and corresponds to one of the memory planes, and the page buffer circuit performs a buffer operation in response to a buffer operation command; and a control logic coupled to the page buffer groups and configured to: for each of the memory planes, provide the buffer operation command to the plurality of page buffer groups, and control performing time periods for the page buffer groups to perform the buffer operation such that some performing time periods among the plurality of performing time periods overlaps.

Memory devices and operation methods thereof, and memory systems for managing page buffer

A memory device includes a peripheral circuit and a memory array coupled with the peripheral circuit. The memory array includes at least one memory block. The peripheral circuit includes at least one row decoder. One memory block is correspondingly connected with one row decoder. The row decoder includes a logic circuit and a level conversion circuit. The logic circuit is configured to generate a first control signal, a second control signal, and a first output signal based on an address signal and a status signal of the memory block correspondingly connected with the row decoder. A level of the second control signal is higher than a level of the first control signal. The level conversion circuit is configured to generate a second output signal based on the first output signal in response to the first control signal and the second control signal respectively.

Memory devices, operation methods thereof, and memory systems

The present disclosure discloses a memory device, a memory system, and a method for operating a memory device, belonging to the field of storage technology. In the present disclosure, by turning off the first switch circuit, turning on the second switch circuit and providing the first voltage to the first node, the first voltage is applied on the second terminal of the drive transistor through the second switch circuit and the source line, the second terminal of the drive transistor is coupled to a control terminal, such that the voltage of the control terminal changes as the voltage of the second terminal changes, since the first voltage is greater than the threshold voltage of the drive transistor, the drive transistor is turned on to trigger the drive transistor to assist the corresponding memory string in performing a gate-induced-drain-leakage (GIDL) erase.

Memory devices, memory systems, and methods for operating memory devices

Devices, systems, and methods for counting a quantity of fail-bits in a memory device using a VFC circuit are disclosed. The VFC circuit can be calibrated via an offset adjustment mechanism to compensate an internal mismatch. The VFC circuit can include a processing unit and a circuit coupled to the processing unit. The processing unit can receive a first signal representing a number of detected fail-bits in the memory array, process the first signal and an offset signal, and generate a second signal representing a quantity of fail-bits. The circuit can receive the first and second signals, determine a difference between the quantity of fail-bits represented by the second signal and the number of detected fail-bits represented by the first signal, adjust the offset signal according to the difference, and provide the offset signal to the processing unit.

Memory system, memory and memory control method

A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of the memory cells in a first memory sub-block of a first memory block, determine verify loop counts of verify operations after programming the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming the memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as for the first memory sub-block of the first memory block, during the non-last pass program, not perform at least the verify operation corresponding to the last of the verify loop counts.

Memory device, memory system, and method for multi-pass programming thereof to reduce programming time

The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

3D NAND memory device and control method thereof

This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Memory device, a memory system and an operation method

In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. The peripheral circuit is configured to program a row of memory cells using a first program voltage and verify the programmed row of memory cells using a verify voltage and a sample voltage smaller than the verify voltage. The peripheral circuit is also configured to obtain a first number of memory cells of the programmed row of memory cells based on the sample voltage. The peripheral circuit is further configured to predict, based on the first number of memory cells and the sample voltage, a second number of memory cells of the programmed row of memory cells that fail to pass the verification.

Memory device and program operation thereof

In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.

Memory device and erase operation thereof

A memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, a controller configured to control a read operation on the array of memory cells, and a row decoder coupled to the word lines and the controller and configured to, in the read operation, induce a coupling effect between a select word line and an adjacent unselect word line of the plurality of word lines, and discharge the select word line to a start read level due to at least the coupling effect.

Methods of enhancing speed of reading data from memory device

A method for programming a memory system including a plurality of memory cells includes performing a first program operation on the plurality of the memory cells. The method also includes identifying a first memory cell and a second set of memory cell from the plurality of memory cells based on threshold voltages of the plurality of memory cells after performing the first program operations. The method further includes performing a second operation on the plurality of the memory cells by applying a first cross voltage to the first memory cell and a second cross voltage to the second memory cell.

Method for programming memory system

A sense circuit of a memory cell includes a first switch, a sense node, a third switch, a connection node, a fourth switch, and a memory cell coupled in series. A boost driver is coupled to the sense node. A second switch and the connection node are coupled in series. The boost driver outputs a first voltage when the first, second, third, fourth switches are turned on. The third switch is then turned off and the boost driver outputs a second voltage higher than the first voltage such that the voltage level at the sense node is not higher than a system voltage. The third switch is turned on, then turned off and the boost driver outputs an intermediate voltage between the first voltage and the second voltage. A state of the memory cell is determined during output of the intermediate voltage.

Sense circuit and sensing operation method in flash memory devices

A memory device includes N rows of memory cells and N word lines coupled thereto, respectively. A method of reading data from the memory device includes: applying a first pre-pulse voltage to an nth word line while applying a second pre-pulse voltage to an adjacent word line adjacent to the nth word line, the second pre-pulse voltage exceeding the first pre-pulse voltage, and n being an integer ranging from 1 to N; grounding the nth word line while maintaining the second pre-pulse voltage on the adjacent word line; pulling a voltage on the nth word line towards a start read level; and prior to the voltage on the nth word line reaching the start read level, driving a voltage on the adjacent word line to the first pre-pulse voltage.

A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.

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Wuhan, China

Ke Liang