Marvell International Limited

Maxtor Corporation

Quantum Corporation

Ke Han

Zining Wu

Pantas Sutardja

Michael Madden

Rui Cao

Hongwei Song

Peter A McEwen

Gregory Burd

Ara Patapoutian

Nitin Nangare

Xueshi Yang

Jeffrey Lee Sonntag

Kevin Dean Fisher

Kelly K Fitzpatrick

Patrick J Moran

Bahjat Zafer

Eduardo Gentile Veiga

Steve Aronson

Ivan Tin-Yam Chan

A system for identifying and compensating for non-linear transition shift in a magnetic medium data storage device is disclosed. The non-linear transition shift compensation system includes a non-linear transition shift estimation module adapted to generate non-linear transition shift estimates for specific bit patterns. The system further includes a pre-compensation module adapted to adjust the temporal spacing of binary transitions written to the magnetic medium based on the non-linear transition shift estimates generated by the non-linear transition shift estimation module for specific bit patterns corresponding to bit patterns appearing in the data being written to the magnetic medium.

Non-linear transition shift identification and compensation

Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response are described. A described system includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit operable to provide a coefficient adjustment to the asymmetry correction circuit to affect asymmetry compensation based on an estimate of nonlinearity derived from the equalized signal and multiple reconstructed ideal channel output values. The reconstructed ideal channel output values can be derived from an output of the discrete time sequence detector and correspond to at least two different discrete times.

Asymmetry correction in read signal

Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

Methods and apparatus for performing interpolated timing recovery

Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response include an integrated circuit device including: an input to receive digital data corresponding to an asymmetry corrected analog signal of a read channel; an input to receive sequence data detected in the digital data; circuitry to generate a coefficient adjustment based on an estimate of non-linearity for the read channel, the estimate derived from the digital data and the sequence data; and an output to provide the coefficient adjustment to affect asymmetry correction of the analog signal.

Systems and methods for detecting and designing enhanced disk sync marks using correlation detection are disclosed. The enhanced sync marks provide better noise immunity and higher detection rates over traditional Viterbi-based detection schemes even with a shorter sync mark length. The disk sync mark may provide optimal noise immunity for a particular target polynomial or a plurality of common target polynomials. The minimum Euclidean distance between a candidate sync mark and a plurality of right-shifted versions of the candidate sync mark is computed and compared with other candidate sync marks. The sync mark with the largest minimum Euclidean distance is then selected as the optimal mark. Systems and methods are also disclosed for detecting and designing a disk sync mark using correlation detection when the polarity of the disk is unknown or time-varying.

Systems and methods for sync mark detection using correlation

Systems and techniques associated with signal processing are described. A described technique includes generating asymmetry vectors that model asymmetry in a received analog signal, including an effect of asymmetry spreading in a read channel and selecting at least two different indicators of asymmetry based on the asymmetry vectors. The technique can include using the selected indicators of asymmetry to compensate for one or more asymmetries associated with the analog signal.

Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response include an integrated circuit device including: an input to receive digital data corresponding to an asymmetry corrected analog signal of a read channel; an input to receive sequence data from a discrete time sequence detector, the sequence data generated by the discrete time sequence detector based on the digital data; an output to provide a coefficient adjustment to affect asymmetry correction of the analog signal; and circuitry to generate the coefficient adjustment based on an estimate of non-linearity for the read channel, the estimate derived from the digital data and the sequence data.

The present disclosure includes apparatus, systems and techniques relating to detecting sync marks. In some implementations, an apparatus includes phase locking circuitry that includes a phase calculator to identify a phase of sampled data, and a phase-locked loop to generate an output signal and phase-lock the generated output signal with the calculated phase of the sampled data to produce a phase-locked signal. The apparatus includes detector circuitry to receive phase information of the phase-locked output signal. The detector circuitry includes a detector to generate a stream of decision bits for the sampled data with each bit in the stream being associated with a different phase. The detector circuitry includes an output selector to select at least one bit from the stream based on the received phase information of the phase-locked output signal.

Spiral servo detection with phase-locked loop (PLL)

Systems and techniques to configure a read channel include, in at least one implementation, an apparatus including: detection circuitry configured to process an input signal from a machine-readable medium to calculate metrics; monitoring circuitry configured to determine a polarity of the input signal based on the metrics and at least one of multiple framings of signal samples of the input signal; and selection circuitry to configure a read channel for the machine-readable medium based on the determined polarity.

Read channel configuration based on polarity determined in accordance with multiple framings of signal samples

Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit that provides a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of non-linearity derived from the equalized signal and an output of the discrete time sequence detector. The estimate can be a least mean squared estimate of the non-linearity in the equalized signal.

Systems and methods for detecting a disk sync mark are provided. The systems and methods for detecting the disk sync mark rely on a detecting the disk sync mark on at least one timing interval. A window of data read bits from a particular disk sector are examined to determine whether they match the disk sync mark. The disk sync mark may be differentiated from expected versions of the disk sync mark using a calculated set of thresholds.

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Fremont, CA, United States of America

Ke Han