Boe Technology Group Co., Ltd.

Hefei Boe Display Technology Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Boe Technology Groupco., Ltd.

Ke Dai

Haipeng Yang

Lei Guo

Chunyang Nie

Peng Hui Jiang

Chunxu Zhang

Yuntian Zhang

Maoxiu Zhou

Liugang Zhou

Liangliang Jiang

Xiaoting Jiang

Yanping Liao

Lixin Zhu

Min Cheng

Ruilian Li

Tao Li

Jianwei Sun

Yulong Xiong

Zhou Rui

Xueqin Wei

Zhonghou Wu

Ming Wang

Li Tian

Zuquan Hu

Yizhan Han

Shenghua Hu

Xiaofeng Yin

Lin Zhang

Qing Ql Li

Zhangtao Wang

Yong Jun Yoon

Bingbing Yan

Liu He

Yunyun Liang

Jiaqing Liu

Zhenlin Qu

Zailong Mo

Yongjun Yoon

Xiaofei Yang

Lei Su

Yue Du

Wenwu Lu

Yu Quan

Zhenyu Zhang

Li Ni Zhang

Taoran Zhang

Hongliang Wang

Mengmeng Li

Wei Sun

Tingliang Liu

Xibin Shao

Zhen Zhang

Zhihua Sun

Yuanhui Guo

Lei Shi

Yingmeng Miao

Da Zhou

Gang Zhou

Yanxia Xin

Zhengdong Zhang

Heng Li

Jingang Liu

Chengpeng Yao

Xiaoliang Cheng

Yawen Zhu

Pengjun Fang

Liwei Zhou

Jiantao Liu

Ming Jin Chen

Qi Liu

Rui Liu

Wei Guo

Xiaoye Ma

Seungmin Lee

Yue Yang

Wenchao Wang

Wen Ji Huang

Jianjun Wang

Yan Yang

Rongcheng Liu

Yiyang Zhang

Hailong Li

Wenjun Liao

Hua Tian

Xipeng Wang

Quan Gan

Long Yan

Linxuan Li

Qiong Zhang

Xiuli Si

Jiawei Qu

Yanting Huang

Hongli Yue

Xutong Chen

Xun Mou

Songyang Jiang

Qing Li

Tianxun Xiu

Qian Zhou

Lihui Han

A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n−m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Display substrate, repair method and display device

A manufacturing method of a display panel, a display panel and a displaying device. The display panel includes an opening area and a non-opening area, and the display panel includes: a first base plate and a second base plate arranged in align with each other, and a liquid-crystal layer between the first base plate and the second base plate. The first base plate includes: a first substrate, and a post spacer provided on one side of the first substrate that is close to the second base plate. The second base plate includes: a second substrate, and a spacing platform provided on one side of the second substrate that is close to the first base plate, wherein the spacing platform is located within the non-opening area. The post spacer is arranged opposite to the spacing platform.

Manufacturing method of display panel, display panel, and displaying device

A driving method of a display panel and a display apparatus provided by embodiments of the present disclosure include: when a display mode switching startup instruction is received, a non-counting state is entered. The display panel is driven to display a first set picture, and a current display mode is switched to a target display mode. When a data mode switching completing instruction is received, a counting state is entered.

Driving method of display panel and display apparatus

A circuit board includes an input side and an output side oppositely arranged, and the output side is configured to electrically connect to a display substrate. The circuit board includes a plurality of signal lines extending in a direction from the input side to the output side. Each of the plurality of signal lines includes a main body and a plurality of output branches. Each of the plurality of output branches is connected to one end of the main body close to the output side and has a same line width. A line width of the main body is greater than a sum of line widths of all the output branches belonging to same signal line.

Circuit board, display substrate and display apparatus

The present disclosure provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate includes a plurality of gate lines () and a plurality of data lines () disposed on a base substrate (), the plurality of gate lines () extend along a first direction, the plurality of data lines () extend in a second direction, the plurality of gate lines () and the plurality of data lines () are intersected to define a plurality of sub-pixels, the sub-pixel includes a thin film transistor (), a pixel electrode () and a common electrode (), the common electrode () in one sub-pixel is connected with the common electrode () in the adjacent sub-pixel through a common connection portion ().

Array substrate and manufacturing method thereof, and display apparatus

A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.

Display panel and display device with non-display area gate lines to match display area gate lines RC load

Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

Array substrate, display panel, and display apparatus

A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion, an orthographic projection of the first compensation end on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate; and a first intermediate portion connecting the first overlapping end and the first compensation end, an orthographic projection of the first intermediate portion on the base substrate is within an orthographic projection of the first spacing on the base substrate.

Thin film transistor, array substrate and display device having slanted gate electrodes

An Embodiment of the present disclosure provide a display substrate, including a base substrate, and a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of common electrodes and a plurality of pixel electrodes on the base substrate. The second scanning lines are parallel to the data lines, and the second scanning lines, the common electrodes and the pixel electrodes are in different layers. The common electrodes are located on a side of the second scanning lines and the data lines away from the base substrate, and on a side of the pixel electrodes proximal to the base substrate. An orthographic projection of one of the data line and the second scanning line on the base substrate is located in a spacer region between adjacent pixel electrodes.

Display substrate and display panel for reducing crosstalk

An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Array substrate and display panel

The present disclosure provides a display device. The display device includes: a liquid crystal display panel; a liquid crystal light control panel located on the light incident side of the liquid crystal display panel; and at least two haze layers located on the light emitting side of the liquid crystal display panel.

Display device

The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q−1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M≥Q>1, 1≤q≤Q, and M, N, Q, q are all positive integers.

Display panel and electronic device

A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.

Display device, gate drive circuit, shift register including two units and control method thereof

A light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes: a first base substrate; and a signal transmission line on a side of the first base substrate close to the first liquid crystal layer and in the peripheral area, the second substrate includes: a second base substrate; and a first black matrix layer on a side of the second base substrate close to the first liquid crystal layer and in the dimming area and the peripheral area; the first black matrix layer has a slot in the peripheral area, and an orthographic projection of at least a part of the slot on the first base substrate is on a side of an orthographic projection of the signal transmission line on the first base substrate, close to the dimming area.

Display module and display apparatus

Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Array substrate, display panel and display device

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Beijing, China

Ke Dai