Siliconware Precision Industries Co., Ltd.

Ke-Chuan Yang

Chin-Te Chen

Feng-Lung Chien

Chih-Shun Chen

Chien-Ping Huang

Chang-Fu Lin

Shih-Kuang Chiu

Chi-Chuan Wu

Jui-Meng Jao

Chao-Dung Suo

Hung-Ming Chang

Po-Hao Yuan

Chia-Yu Hung

A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.

Circuit board structure and method for fabricating the same

A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via a thermal interface material, such as a solder material, wherein a groove is formed on the heat sink around the bonding area of the thermal interface material, and a blocking layer, such as a metal oxide layer, is formed on the surface of the groove to reduce the wetting capability of the thermal interface material, thus further prevents the thermal interface material from wetting the groove in the fusion process performed the thermal interface material, therefore, it ensures the thermal interface material has sufficient thickness for forming solder bonding between the heat sink and the flip chip semiconductor chip.

Heat-dissipating structure and heat-dissipating semiconductor package having the same

A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is formed on the upper surface of the inner end of each lead, making the inner end shaped as a stepped structure. The depth of the recessed portion is equal to a height of a reflow-collapsed solder bump that is for electrically connecting a chip to the lead. At least one chip is electrically connected to the leads in a flip-chip manner via a plurality of solder bumps bonded to the recessed portions. An encapsulation body is formed to encapsulate the lead frame, chip and solder bumps, with the lower surfaces of the leads being exposed from the encapsulation body.

Flip-chip semiconductor package with lead frame and method for fabricating the same

A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.

Photosensitive semiconductor package and method for fabricating the same

A semiconductor device with under bump metallurgy (UBM) and a method for fabricating the semiconductor device are provided, wherein a passivation layer is deposited on a surface of the semiconductor device where a plurality of bond pads are disposed, and formed with a plurality of openings for exposing the bond pads. A first metal layer is deposited over part of each of the bond pads and a portion of the passivation layer around the bond pad; then, a second metal layer is formed over the first metal layer and part of the bond pad uncovered by the first metal layer; subsequently, a third metal layer is formed over the second metal layer to thereby fabricate a UBM structure. Finally, a solder bump is formed on the UBM structure so as to achieve good bondability and electrical connection between the solder bump and UBM structure.

Semiconductor device with under bump metallurgy and method for fabricating the same

A fabrication method for strengthening flip-chip solder bumps is provided to form a solder bump on a UBM (under bump metallurgy) structure formed over a semiconductor chip, which can prevent the UBM structure against oxidation and contamination and also enhance bondability between the solder bump and UBM structure, thereby improving reliability for packaging the semiconductor chip. This fabrication method is characterized in that before forming the solder bump, a dielectric layer made of BCB (benzo-cyclo-butene) or polyimide is deposited on the UBM structure, and used to protect the UBM structure against oxidation and contamination. Further, before forming the solder bump, a plasma-etching process is performed to remove the dielectric layer; the plasma-etching process is environmental-friendly without having to use a chemical solvent.

Fabrication method of strengthening flip-chip solder bumps

A non-leaded semiconductor package and method of fabricating the same is proposed, which can be used for the fabrication of a non-leaded type of semiconductor package, such as a CQFN (Carrierless Quad Flat No-lead) package. The proposed semiconductor packaging technology is characterized by the use of a metal plate as provisional chip carrier during fabrication and by the use of RDL (Redistribution Layer) technology to provide internal electrical interconnections between the I/O pads of the packaged chip and the non-leaded external electrical contacts. These features allow the fabrication of the CQFN package to be implemented without the use of bonding wires for internal electrical connections and without the use of substrate as a permanent chip carrier.

Non-leaded semiconductor package and method of fabricating the same

A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.

Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer

A solder-pump fabrication method is proposed, which is used for the fabrication of solder bumps with high coplanarity over a semiconductor chip for flip-chip application. The proposed solder-bump fabrication method is characterized in the use of a two-step solder-bump fabrication process, including a first step of electroplating solder over UBM (Under Bump Metallization) pads to a controlled height still below the topmost surface of the mask, and a second step of screen-printing solder paste over the electroplated solder layer. The combined structure of the electroplated solder layer and the printed solder layer is then reflowed to form the desired solder bump. Since the proposed solder-bump fabrication method allows the solder material electroplated and printed over the UBM pads to be confined within the mask openings and never exceed the topmost surface of the mask, the resulted solder bumps would not be bridged to neighboring ones. Moreover, the proposed solder-bump fabrication method allows all the resulted solder bumps to be substantially equally sized to achieve high coplanarity.

Growing community of inventors

Taichung, Taiwan

Ke-Chuan Yang