Taiwan Semiconductor Manufacturing Comp. Ltd.

Ke-Chia Tseng

Chih-Han Lin

Chao-Cheng Chen

Ming-Ching Chang

Shih-Yao Lin

Kuei-Yu Kao

Chen-Ping Chen

Chih-Chung Chiu

Hsien-Chung Huang

Chen-Yui Yang

A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Semiconductor devices and methods of fabrication thereof

A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Semiconductor devices including dummy gate dielectric layer and methods of manufacturing thereof

Semiconductor devices and methods of manufacturing thereof

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Hsinchu, Taiwan

Ke-Chia Tseng