Nec Corporation

Mitsui Petrochemical Industries, Ltd.

Sumitomo Heavy Industries, Ltd.

Kazuyuki Yamasaki

Kojiro Kan

Teiichiro Nishizaka

Kimio Yamamoto

Masanobu Watanabe

Yoshio Nakayama

Kiyokazu Hashimoto

Hironori Sakamoto

Kazutaka Otsuki

Kenji Hibino

Tetsuji Togami

Takehiko Kitamura

Fukashi Kagawa

Masao Kunitou

Tonomi Egawa

A semiconductor ROM device which enables to obtain a reference current which can securely distinguish data stored in a memory cell in a multilevel mask ROM for storing multilevel data of three or more levels per memory cell. The device comprises a memory cell in which a threshold voltage is set up corresponding to an amount of ions injected to a channel region of a cell transistor and multilevel data of three or more levels are stored, a reference cell for generating the reference current for comparing with a current read out from the memory cell, and dummy cells disposed adjacent to the reference cell. In the channel region of the reference cell and the channel region of the dummy cell, ions are injected simultaneously to set up the equal threshold voltages both in the reference cell and the dummy cell.

Semiconductor memory device having multilevel memory cell and method of manufacturing the same

The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit uses a control signal CA T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit as a latch pulse SAL A, and to a second latch group within the latch circuit as a latch pulse SAL A, respectively. Based on a control signal YS &tilde;YS input from a column decoder circuit , a Y selector is connected to a sense amplifier circuit via Y switches connected to the corresponding digit lines. The sense amplifier circuit comprises sense amplifiers, and performs data evaluations of the signal YD &tilde;signal YD from the Y selector. A latch circuit latches a data signal DT &tilde;data signal DT from the sense amplifier circuit into a first latch group and a second latch group via latch signals SAL and SAL respectively.

Semiconductor memory device and method for reading data

When a cell of a memory cell array (C,and C,) located at a position further from the word select line driver is selected, data that is read from the memory cell array (C,, C,) is sent via only sense amplifier circuits (S,, S,) to the output buffer circuit (OB), while data from the other memory cell array (C,&tilde;C,) are sent via the sense amplifier circuits (S,&tilde;S,), the error detection circuit (ECC,), the syndrome decoder circuit (ECC,) and the error correction circuits (CR,&tilde;CR,) to the output buffer circuit (OB). Data are output while bypassing the ECC circuits for the memory cells (C,, C,) of which word select lines have larger resistance and capacitance that cause a significant delay in the reading by the sense amplifier compared to reading of the memory cells located near the start point of the word select line (critical read cell). For the memory cells (C,&tilde;C,) of which word select lines have smaller resistance and capacitance of which reading by the sense amplifier is equivalent to that of the memory cells located near the start point of the word select line (critical read cell), data are output after correcting errors in the ECC circuits. With this constitution, the masked ROM that combines high-speed access capability and relieving effect and is advantageously applied to a large-capacity masked ROM with built-in ECC can be achieved.

Semiconductor memory device with improved error correction

A word level generator in a multiple-valued mask programmable read only memory semiconductor device having a plurality of kinds of mask programmable read only memory cells having a plurality of distributions in number of the mask programmable read only memory cells versus variation of actual threshold voltages from predetermined threshold voltages. The distributions are separated from each other and do not overlap each other. The word level generator generates a word level which is between a maximum voltage level of lower one of adjacent two of the distributions and a minimum voltage level of higher one of the adjacent two of the distributions, so that all of the mask programmable read only memory cells are permitted to show correct ON/OFF operations for application of different word level voltages, whereby only correct data are obtained from the multiple-valued mask programmable read only memory semiconductor device.

Multiple-valued mask programmable read only memory semiconductor device

When a data bit is read out from a semiconductor read only memory device, a current-mirror type sense amplifier is electrically connected through a bit line, a first selector, a selected memory cell and a second selector to a discharging line so as to check a potential drop on the bit line, and each of the first and second selectors selectively connects the bit line or the discharging line to eight columns of memory cells by increasing the component switching transistors thereof so as to space the bit line from the discharging line, thereby increasing a margin for a bit line contact.

Semiconductor memory device having bit lines widely spaced without

In a semiconductor memory comprising one main bit line D1, a pair of main ground lines VG1 and VD2, a plurality of memory cell banks to be selectively connected to the main bit line D1 and the main ground lines VG1 and VD2, and a plurality of word lines W1 to Wn extending through the memory cell banks, each of the memory cell banks includes a plurality of wirings L1, L2, L3, L4 and L5 located in parallel to each other, and a threshold of a block selection transistor BT11 connected between the main bit line D1 and the wiring L3, is lower than that of block selection transistors BT12 and BT13 connected between the main bit line D1 and the wiring L2 and between the main bit line D1 and the wiring L4, respectively.

Semiconductor memory having a plurality of memory banks and sub-bit

A process for the preparation of substrate for optical disk characterized in that pellets of 4-methyl-1-pentene polymer or copolymer having a melt flow rate (MFR), as measured according to ASTM D1238 under a load of 5 kg and at a temperature of 260.degree. C., of 240-1200 g/10 min, and a melting point as measured by means of DSC of 234.degree.-240.degree. C., are injection molded into the substrate under the conditions where a temperature of at least part of a cylinder is 320.degree.-370.degree. C. and a mold temperature is not more than 55.degree. C.

Process for the preparation of substrates for optical disk

A membrane filter material formed from a solvent resistant bimaleimide polymer which is formed by polymerizing a bismaleimide compound with a perhydrodiaza-type heterocyclic compound and has a main structural skeleton represented by the following formula: ##STR1## wherein R.sub.1, R.sub.2, R.sub.3 and R.sub.4 represents a lower carbon chain which is linear or contains a methyl group or ethyl group on the side chain, R.sub.5 represents a divalent group containing an aromatic ring, Y is &gt;R&lt; or &gt;N--R--N&lt; in which R is a lower carbon chain, and m is 0 or 1. This bismaleimide polymer can be a membrane filter material having an excellent organic solvent resistance. When this polymer is formed into a hollow fiber or plain film, a high separating and filtering capacity and an excellent organic resistance can be attained. A membrane filter material having an enhanced organic solvent resistance is provided by preparing the bismaleimide polymer by reacting the bismaleimide compound and perhydrodiaza-type heterocyclic compound in a halogen-containing organic solvent in the present of a small amount of a phenol.

Membrane filter material having excellent organic solvent resistance,

A membrane filter material formed from a solvent resistant bismaleimide polymer which is formed by polymerizing a bismaleimide compound with a perhydrodiaza-type heterocyclic compound and has a main structural skeleton represented by the following formula: ##STR1## wherein R.sub.1, R.sub.2, R.sub.3 and R.sub.4 represents a lower carbon chain which is linear or contains a methyl group or ethyl group on the side chain, R.sub.5 represents a divalent group containing an aromatic ring, Y is &gt;R&lt; or &gt;N--R--N&lt; in which R is a lower carbon chain, and m is 0 or 1. This bismaleimide polymer can be a membrane filter material having an excellent organic solvent resistance. When this polymer is formed into a hollow fiber or plain film, a high separating and filtering capacity and an excellent organic resistance can be attained. A membrane filter material having an enhanced organic solvent resistance is provided by preparing the bismaleimide polymer by reacting the bismaleimide compound and perhydrodiaza-type heterocyclic compound in a halogen-containing organic solvent in the presence of a small amount of a phenol.

An electret article comprising an even number of electret plastics films laminated together, with the surfaces of the same polarity facing each other, said laminate having the same polarity on both external sides. It keeps its high surface charge density. It will find use in such applications as acoustic materials, filters, and medical supplies.

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Tokyo, Japan

Kazuyuki Yamasaki