Renesas Electronics Corporation

Kazuyuki Umezu

Tomoaki Uno

Koujirou Matsui

Takehiko Sakamoto

Junichi Nakamura

Nobuyuki Shirai

Ryo Kanda

Hirokazu Kato

Yasushi Nakahara

Yoshinori Kaya

Tetsu Toda

Tomonobu Kurihara

Hideo Numabe

Takahiro Nagatsu

Ryotaro Kudo

Koji Tateno

Hideo Ishii

Takeshi Iijima

Makoto Koshimizu

Koji Saikusa

Atsushi Tachigami

Hideki Niwayama

Hiroki Soeda

A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

Semiconductor device and method for manufacturing same

A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Semiconductor device

A control electrode GEis formed in a lower portion of a trench TRformed in a semiconductor substrate SUB, and a gate electrode GEis formed in an upper portion inside the trench TR. An insulating film Gis formed between the control electrode GEand a side wall and a bottom surface of the trench TR, an insulating film Gis formed between the side wall of the trench TRand the gate electrode GE, and an insulating film Gis formed between the control electrode GEand the gate electrode GE. A region adjacent to the trench TRincludes an n-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GEis not connected to a wiring connected to the gate electrode GE, and is not connected to a wiring connected to the n-type semiconductor region NR for a source.

A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.

Semiconductor device, power control device and electronic system

In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.

Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.

Power supply device

Growing community of inventors

Kanagawa, Japan

Kazuyuki Umezu