Hitachi, Ltd.

Kabushiki Kaisha Nihon Micronics

Renesas Electronics Corporation

Renesas Technology Corp.

Guala Technology Co., Ltd.

Hitachi Ulsi Engineering Corp.

Kazuyuki Tsunokuni

Yuichi Hamamura

Kazumasa Yanagisawa

Hideo Aoki

Aritoshi Sugimoto

Eiichi Murakami

Takayuki Oshima

Hizuru Yamaguchi

Kan Takeuchi

Hisao Asakura

Takaaki Kumazawa

Takako Funakoshi

Kousuke Okuyama

Tomokazu Saito

Takashi Tonokawa

Akira Nakazawa

Tatsuo Inoue

Kazuo Nojiri

Kiyoyasu Hiwada

Yuki Sato

Tatehito Usui

Tetsuo Ono

Masayuki Kojima

Masato Ikegawa

Keiji Okamoto

Shigefusa Chichibu

Takuo Kudoh

Harutada Dewa

Nobuyuki Mise

Chizu Matsumoto

Kazunobu Kojima

Hirohisa Usuami

Hikaru Takano

Tomokazu Saitoh

Daisuke Hasegawa

Taku Higuti

Yoshiyuki Tsunoda

Yutaka Kosaka

Juri Ogasawara

Kunihiko Nakada

Kohji Tonokawa

A secondary battery includes: a solid electrolyte layer which contains a tantalum oxide as a solid electrolyte; a positive-electrode active material layer which is disposed on an upper surface of the solid electrolyte layer and contains a nickel hydroxide (Ni(OH)) as a positive-electrode active material; and a negative-electrode active material layer disposed on a lower surface of the solid electrolyte layer so as to be opposite to the positive-electrode active material layer and containing a titanium oxide (TiO) or a titanium oxide (TiO) and a silicon oxide (SiO) as a negative-electrode active material. There is provided a secondary battery capable of improving electricity storage performance by improving a self-discharge.

Secondary battery

A secondary battery includes: a first oxide semiconductor having a first conductivity type; a first charging layer disposed on the first oxide semiconductor layer, and composed by including a first insulating material and a second oxide semiconductor having the first conductivity type; a second charging layer disposed on the first charging layer; a third oxide semiconductor layer having a second conductivity type disposed on the second charging layer; and a hydroxide layer disposed between the first charging layer and the third oxide semiconductor layer, and containing a hydroxide of a metal constituting the third oxide semiconductor layer. The highly reliable secondary battery is capable of improving an energy density and increasing battery characteristics (electricity accumulation capacity).

An intermediate structure unit for a secondary cell according to the present invention is the intermediate structure unit for a secondary cell having a secondary cell and a test structure unit on a common substrate. Each of the secondary cell and the test structure unit includes a first electrode layer and a second electrode layer. A plurality of layers are layered at the secondary cell between the first electrode layer and the second electrode layer. The plurality of layers include at least a metal oxide semiconductor layer and a charging layer. A party of the plurality of layers is formed at the test structure unit between the first electrode layer and the second electrode layer.

Intermediate structure unit for secondary cell and method for manufacturing secondary cell

A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.

Secondary battery mounted chip manufacturing method

A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer. Secondary battery and circuit are formed into integrated structure by forming the uppermost part of circuit having multilayer wiring into secondary battery structure on upper part of circuit surface subjected to passivation, forming secondary battery directly stacked by making uppermost wiring layer of multilayer wiring part of circuit in a surface structure to be used in common, or forming secondary battery on rear surface of substrate having the circuit formed thereon.

Secondary battery-mounted circuit chip and manufacturing method thereof

A charging/discharging device performs charging and discharging on a plurality of secondary cells concurrently in parallel, without adopting a power source having an extremely high current supply capacity. A plurality of switching units controlled by a switching control unit are interposed respectively between the secondary cells and each of a plurality of charging power lines and discharging power lines. A power unit applies voltages having mutually-different voltage values and the switching control unit controls switching so that the respective secondary cells are connected cyclically in predetermined order to the charging and discharge power lines.

Charging/discharging device

In a managing system for a semiconductor manufacturing apparatus, a predicting unitpredicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.

Defective-ratio predicting method, defective-ratio predicting program, managing method for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device

In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Method of manufacturing a semiconductor integrated circuit device

A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Semiconductor integrated circuit device

A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

Method for test conditions

Photomask for test wafers

System for testing electronic devices

Growing community of inventors

Tokyo, Japan

Kazuyuki Tsunokuni