Fujitsu Corporation

Konica Corporation

Goh Shoji Co., Inc.

Kazuyuki Shimizu

Yuji Oinaga

Katsumi Onishi

Toshiaki Kitamura

Minoru Koshino

Saburo Kaneda

Fujio Ikegami

Terutaka Tateishi

Toshio Hayashi

Satoshi Harada

Koichi Inoue

Hiroshi Takahashi

Takeshi Tanaka

Naomi Matsumura

Takamitsu Tsuchimoto

Makoto Yoshida

Yoshihiro Mizushima

Kiyosumi Sato

Masazi Yoshimura

Hitoshi Mitake

Nakaya Nakano

Shigemi Kamimoto

Hajime Nonogaki

Yoshimasa Hiruma

Tatsuo Urakawa

Hiromi Tanaka

Yukichi Ikuta

Masato Fujimori

Eiichi Morita

A connector device includes a main body having a plug section. The main body accommodates therein two contact members, a bidirectional diode-thyristor, and a distal end portion of a signal-transmission cable connected with an external electronic equipment. The two contact members are connected with two terminals of the thyristor and two conductor wires of the signal-transmission cable, to thereby obtain a modular plug with overvoltage protection. By inserting the modular plug into a modular jack, the external electronic equipment is connected with a communication line. If an overvoltage is applied to the communication line, the thyristor is rendered conductive to absorb the overvoltage, so that the electronic equipment is protected from the overvoltage. In place of designing the connector plug to hold the distal end portion of the signal-transmission cable, the connector body may be formed with a socket section which receives an external modular plug, to thereby obtain a modular adapter with overvoltage protection which is used to connecting a modular plug with a modular jack.

Connector device with overvoltage protection

The present invention is to provide an apparatus for coating an advancing web on a backup roller Using a coating roller, which enables one to measure and control a coating gap between a lip surface of a coating die and the coating roller. The apparatus includes an extended portion which extends outward from each end of a slit portion of the coating die and has a reference surface parallel to the lip surface, the coating die is slidably located on a frame, a distance sensing means is fixed on each side of the coating roller, a distance is measured from the distance sensing means to the surface of the extended portion and the coating gap is controlled by sliding the coating die in a radial direction of the coating roller. Coating material is thereby controllably transferred from the coating roller to the web.

Coating apparatus with coating die

To provide a small-sized and inexpensive flash lighting circuit for a camera capable of fully reducing red eyes reflection, a sub capacitor, a main capacitor and a flash discharge tube are connected in parallel to a DC-DC converter, whereby the sub capacitor is directly connected to the DC-DC converter, the main capacitor is connected to the above parallel connected line through a first diode which prevents the charge of the main capacitor from flowing into the flash discharge tube to allow preliminary lighting, the thyristor for changing over preliminary lighting and main lighting is disposed between the main capacitor and the flash discharge tube on a bypass line led out from the junction point of the main capacitor and the first diode, and a second diode, which prevents the charge of the main capacitor flowing into the sub capacitor after the sub capacitor has been first discharged at the time of main lighting, is disposed on the above parallel connected line between the cathode of the thyristor and the sub capacitor.

Flash lighting circuit

A position setting apparatus for positioning a drum so that it may be uniformly coated with a photosensitive coating liquid to produce a photoreceptor, wherein the position of the drum is set by centripetally blowing a pressurized fluid from a fluid outlet means directly against the drum. The drum is positioned by the balance of the pressure of the blown fluid, and the surface of the drum is thereby protected from scratching as no mechanical device is required to touch the drum during positioning.

Photoreceptor-drum-positioning apparatus

An electronic flash device includes a flash discharge tube, an IGBT, connected to the flash discharge tube, for controlling light emission, a trigger means for driving the flash discharge tube, an AC voltage generating means having an oscillation transformer for generating an AC voltage from an input voltage, and a power supply section for generating a gate drive voltage for the IGBT from a counter electromotive voltage generated at a terminal of a winding of the oscillation transformer. The electronic flash device further includes an IGBT drive voltage generating means, a first resistor connected between the IGBT drive voltage generating means and a gate of the IGBT, a capacitor having a terminal connected to the IGBT drive voltage generating means and having a capacitance larger than an electrostatic capacitance across the gate and an emitter of the IGBT, a second resistor having a terminal connected to the other terminal of the capacitor and the other terminal connected to the gate of the IGBT and a resistance smaller than that of the first resistor, and a third resistor connected between a ground terminal and a connection terminal between the IGBT drive voltage generating means and the first resistor.

Electronic flash device

A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse sets a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

System for controlling operation of processor by adjusting duty cycle of

A storage-protection-check circuit includes a storage key corresponding to the unit area of a storage region, the storage key being stored in a key storage. The value of the access request key having an access request corresponding to the storage region is checked. When the access request key has a specified value, the storage region is accessed without reading the storage key out of the key storage.

Method and circuit for checking storage protection by pre-checking an

A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse makes a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

Data processing system having a performance control pulse with a

A machine check processing system which includes: an error correcting circuit for correcting a correctable error generated during data processing; an error data storage for storing error data which relates to the correctable error; a central processing unit (CPU) for controlling the error correcting circuit and the error data storage; and a service processing unit (SVP) for operating and controlling the error correcting circuit, the error data storage, and the CPU. The CPU includes an error data freezing circuit for freezing error data stored in the error data storage when a correctable error occurs, and a machine check record request signal generator for generating a machine check record request signal when a correctable error occurs. The SVP comprises an error data saving device for carrying out a saving process to save the frozen error data stored in the error data storage in response to the machine check record request signal, an error data analyzing circuit for carrying out an error analyzing process and a freeze release circuit for releasing the error data stored in the error data storage from a frozen state after the error data saving device saves the error data. At least a part of the saving process and the error analyzing process are automatically carried out substantially simultaneously with the operation of the CPU, without a machine check interruption.

Machine check processing system

An erroneous microinstruction and related preceding microinstructions are subjected to a so-called retry operation so as to restore the microprogram-controlled unit and correct the error. The retry operation is carried out under an interlock mode, in which both detection and correction occur prior to processing for each microinstruction. At the same time, an address specifying a thus detected erroneous microinstruction is recorded. When the recorded address is next generated, the interlock mode is automatically entered for the erroneous microstruction only.

Method for recovering from error in a microprogram-controlled unit

In a system which is provided with a key storage having stored therein main storage keys respectively corresponding to pages into which a main storage is split, each main storage key having at least a reference bit indicating whether the corresponding page is being accessed and a change bit indicating whether information has been written in the page, and in which a parity bit is added to each of the reference bits and the change bits to form the main storage key. There are provided a detecting device for detecting a parity error in a pair of the reference bit and the parity bit and a pair of the change bit and the parity bit when the main storage key is read out, and a device for rewriting the main storage key after setting the reference bit to a '1' indicating the corresponding page is being accessed and adding a new parity bit '0' to the reference bit when a parity error is detected by the detecting device in the pair of the reference bit and the parity bit and after setting the change bit to a '1' indicating a write in the corresponding page and adding an new parity bit '0' to the change bit when a parity error is detected in the pair of the change bit and the parity bit, thereby controlling the saving of the pages of the main storage into external storage.

Key storage error processing system

A synchronizing circuit provides a plurality of signal transmission paths having different delay times in the line for transmitting signals. A pilot signal circuit has a pilot signal generator circuit which operates on the sending side, and a pilot signal is sent via one of the paths having a different delay time to a plurality of latch circuits on the receiving side. The output of each of the latch circuits is compared by a predicting circuit, so as to predict the phase difference between the clock signals of sending clock system and the receiving clock system. According to the result of this prediction, the signal transmission path having the optimum delay time is selected, so as to transmit the received signal that has been synchronized to the latch on the receiving side.

Synchronizing circuit

Virtual machine system

An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.

Address control system for software simulation

In a data processing system having a plurality of virtual address spaces, a virtual address is translated into a real address for accessing a main memory and the translation result is stored in a translation lookaside buffer, as in a processing system having a single virtual address space. Thereafter, in the case of the same virtual address as the above, the translation lookaside buffer is retrieved to translate the virtual address into a real address. Generally, even in the case of the same virtual addresses, if their virtual address spaces are different, the virtual addresses are translated into different real addresses. However, a control program, a control table or a common subroutine is provided in a common area in which the coordination of virtual and real addresses is always constant even in the case of different virtual address spaces. To enhance the efficiency of utilization of the translation lookaside buffer, common area indicating means is provided, by which the coordination of virtual and real addresses on the translation lookaside buffer is registered so that it can be used in common to a plurality of virtual address spaces.

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Tokyo, Japan

Kazuyuki Shimizu