Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Kazuyuki Sawada

Nobuo Aoi

Kunimasa Takahashi

Gaku Sugahara

Koji Arai

Yuji Harada

Makoto Kitabatake

Masao Uchida

Osamu Kusumoto

Kenya Yamashita

Takaaki Higashida

Masahiko Niwayama

Saichirou Kaneko

Mamoru Inoue

Shigeru Namiki

Toshiyuki Fujioka

Tetsuo Imada

Masahiro Hagio

Hiroshi Yamamoto

Hisashi Ogawa

Tsutomu Fujita

Tsutomu Kiyosawa

Yoshimi Shimizu

Kohsaku Yano

Toshihiko Uno

Yuki Tomita

Masaaki Okita

A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall. The first portion of the gate insulating film is thicker than a third portion of the gate insulating film located on the upper surface of the SiC layer. And an end portion of the gate electrode is located on the upper corner region.

Silicon carbide semiconductor element and method for fabricating the same

A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity type formed in the semiconductor substrate; a low concentration source region of a second conductivity type formed in the semiconductor substrate and spaced apart from the low concentration drain region; and a high concentration source region of a second conductivity type having a diffusion depth deeper than that of the low concentration source region. A diffusion depth of the low concentration source region is equal to that of source/drain regions of the MOSFET.

Semiconductor device and method for fabricating the same

Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.

Semiconductor device with substrate having increased resistance due to lattice defect and method for fabricating the same

An ion-through regionis provided as a first opening in a passivation filmon a source electrodeand a drain electrode. The passivation filmis coated with a sealing resin to package the semiconductor device. At this point, the ion-through regionis filled with the sealing resin to put the sealing resin into direct contact with the source electrodeand the drain electrode. With this structure, movable ions accumulated at an interface of the sealing resin with the passivation filmin a high temperature and high humidity atmosphere are discharged to the source electrodeand the drain electrodevia the ion-through regionand thus do not influence an N-type extended drain region. Therefore, the drain breakdown voltage can be improved.

Semiconductor device having a high breakdown voltage transistor formed thereon

A material containing, as a main component, an organic silicon compound represented by the following general formula:RSi(OR)(where Ris a phenyl group or a vinyl group; Ris an alkyl group; and x is an integer of 1 to 3) is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component. As the organic silicon compound where Ris a phenyl group, there can be listed phenyltrimethoxysilane or diphenyldimethoxysilane. As the organic silicon compound where Ris a vinyl group, there can be listed vinyltrimethoxysilane or divinyldimethoxysilane.

Method of forming interlayer insulating film

Process and apparatus of producing optical disk and process of producing substrate

A material containing, as a main component, an organic silicon compound represented by the following general formula:

A method of forming a contact structure comprising a first step whereby a contact hole is formed with an etching stopper film by way of self-alignment, a second step whereby the etching stopper film is removed from the contact hole, and a third step of metallization, whereby unnecessary intermediate film layers are removed from the connected regions.

Method of forming contact structure

A method is provided for producing a semiconductor device characterized by filling hollows having a high aspect ratio with a semiconductor film doped with impurities as dopants and an undoped semiconductor film, given that the doped polycrystalline Si film produced by thermal decomposition of reactive gases mixed with impurity gases and the undoped polycrystalline Si film produced by thermal decomposition of reactive gases containing no impurity gas have different step coverage characteristics from each other. The method allows uniform distribution of dopants as well as improvement of processing throughput by forming sequentially the two types of semiconductor films in one reaction chamber.

Method for producing a semiconductor device by filling hollows with

Growing community of inventors

Osaka, Japan

Kazuyuki Sawada