Kabushiki Kaisha Toshiba

Kazuyuki Omote

Takeji Tokumaru

Tsuneaki Kudou

Tohru Sasaki

Jun Iwamura

A barrel shifter is provided with a plurality of shifters arranged in series for combining pieces of data A, B respectively represented by a sequence of 32-bit, 16-bit, or 8-bit binary digits into a piece of combined data C and shifting the combined data C by some bits. The shifters consists of a 16-bit shifter, 8-bit shifter, 4-bit shifter, 2-bit shifter, and two 1-bit shifters. The 32-bit data A, B are shifted in the 16-bit shifter. The 16-bit data B is shifted in the 16-bit shifter to connect with the 16-bit data A. The 8-bit data B is shifted in the 16-bit shifter to approach the 8-bit data B. The combined data C formed by connecting the 32-bit data A, B or the 16-bit data A, B in the 16-bit shifter is shifted in the following shifters. The 8-bit data B in the 16-bit shifter is shifted in the 8-bit shifter to connect with the 8-bit data A so that the combined data C is formed. The combined data C formed by connecting the 8-bit data A, B in the 8-bit shifter is shifted in the following shifters.

Barrel shifter for combining pieces of data into a piece of combined

A barrel shifter for successively shifting reference data in a plurality of stages includes a wiring network for every stage to shift the reference data to produce shifted data and selectors connected to the wiring network for every stage except for a specific stage to output either the reference data or the shifted data as new reference data to a following stage while distorting the electric waveform of the selected data. The barrel shifter also includes complex clocked inverters connected to the wiring network in the specific stage to output either the reference data or the shifted data as new reference data to a following stage while correcting the electric waveform of the selected data.

Barrel shifter for data shifting

A bus driver in which at least two P channel MOS transistors and at least two N channel MOS transistors are employed and these are respectively connected in series. A data signal is inputted into a gate of one of the P channel MOS transistors, an inverted input of an enable signal is inputted into a gate of the other of the P channel MOS transistors, the enable signal is inputted into a gate of one of the N channel MOS transistors and the data signal is also inputted into a gate of the other of the N channel MOS transistors. Further, an output signal is outputted from a connection point of the P channel MOS transistors and the N channel MOS transistors. Also disclosed is another embodiment of a bus driver in which an inverted signal of an enable signal is inputted into the other of the P channel MOS transistors through an inverter.

Integrated circuit using bus driver having reduced area

An integrated standard cell consisting of a plurality of standard cells each having a logical area, at least one power supply line, and one ground line, which further includes two clock signal lines for supplying clock signals. These signals are formed within each standard cell and are provided outside of the power supply line and the ground line, in parallel thereto. The two clock signal lines are connected to the logical area through each shunt line which substantially extends in the vertical direction to the clock signal lines. With this construction, a quantitative prediction for the time delay of clock signals which propagate in the clock signal lines becomes easy, thereby preventing any skew of the clock signals from occurring.

Growing community of inventors

Yokohama, Japan

Kazuyuki Omote