Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Other

Elpida Memory, Inc.

Mitsubishi Denki Kabushiki Kaisha

Hitachi Device Engineering Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Vsli Engineering Corp.

Kazuyuki Miyazawa

Jun Etoh

Ryoichi Hori

Kazuyoshi Oshima

Kazuhiko Kajigaya

Hidetoshi Iwai

Yasunori Yamaguchi

Yasuhiro Kasama

Eiji Miyamoto

Masashi Horiguchi

Akira Endo

Takashi Yamazaki

Yuji Sakai

Hiroshi Yoshioka

Tetsurou Matsumoto

Makoto Morino

Shinji Udo

Shinichi Ikenaga

Sinichi Miyatake

Mitsuhiro Takano

Manabu Tsunozaki

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Masamichi Ishihara

Katsutaka Kimura

Tetsuya Tsujikawa

Yasushi Takahashi

Hiroshi Sato

Satoshi Oguchi

Naoki Yamada

Katsuhiro Shimohigashi

Tetsuro Matsumoto

Masaya Muranaka

Kousuke Okuyama

Toshiyuki Sakuta

Hisao Katto

Hiromi Matsuura

Kazumichi Mitsusada

Hiroyuki Uchiyama

Kunihiko Nishi

Gen Murakami

Aizo Kaneda

Shozo Nakamura

Masao Mitani

Hisashi Nakamura

Yoshihisa Koyama

Toshihiro Tanaka

Hitoshi Miwa

Masayuki M Nakamura

Yasuhiro Nakamura

Shigeru Tanaka

Hidetomo Aoyagi

Shigetoshi Sakomura

Haruo Ii

Takeshi Kizaki

Takeshi Sakata

Riichiro Takemura

Tomonori Sekiguchi

Masataka Kato

Shinichi Miyatake

Toshitugu Takekuma

Toshio Sasaki

Atsushi Ohba

Masaharu Kubo

Takesada Akiba

Kanji Oishi

Atsuyoshi Koike

Hiroshi Kawamoto

Hiroshi Otori

Yuji Yokoyama

Kazuya Ito

Shoji Wada

Yoshitaka Kinoshita

Toshio Maeda

Fumiyuki Kanai

Takayuki Yoshitake

Osamu Sakai

Masanori Tazunoki

Yoshiaki Ouchi

Toshitugu Takemuma

Satoru Koshiba

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Non-volatile multi-level semiconductor flash memory device and method of driving same

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

Non-volatile multi-level, semiconductor flash memory device and method of driving same

A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell&#xb7;two cells/bit method has a twin cell structure employing a one-intersection 6Fcell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

Semiconductor memory device

A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Semiconductor integrated circuit device

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell&middot;two cells/bit method has a twin cell structure employing a one-intersection 6F cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

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Iruma, Japan

Kazuyuki Miyazawa