Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Holdings Corporation

Kazuyuki Kouno

Masayoshi Nakayama

Reiji Mochida

Takashi Ono

Yuriko Hayata

Takanori Ueda

Keita Takahashi

Hoshihide Haruyama

Yasuhiro Tomita

Yasuo Murakuki

Takafumi Maruyama

Hitoshi Suwa

Akifumi Kawahara

Yoshiaki Nakao

Norio Hattori

Yuriko Ishitobi

A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Neural network computation circuit including non-volatile semiconductor memory element

A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.

Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.

Neural network computation circuit including semiconductor memory element, and method of operation

A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.

Neural network computation circuit including semiconductor storage elements

A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.

Variable resistance non-volatile memory device

A semiconductor memory device includes a first select line and a second select line. A first memory element among a plurality of memory elements has a first top electrode and a first bottom electrode. The first top electrode is connected to the first select line and the first bottom electrode is connected to the second select line. A second memory element among the plurality of memory elements, which is disposed adjacent to the first memory element, has a second top electrode and a second bottom electrode. The second top electrode is connected to the first select line, and the second bottom electrode is connected to the first select line without passing a resistive element of a memory element other than the second memory element.

Semiconductor memory device

A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

Nonvolatile semiconductor storage device including cell transistor performance measuring cells

A nonvolatile semiconductor memory device includes: a memory cell (MC) including a cell transistor (TC) and a variable resistance element (RR); a memory cell (MC) including a cell transistor (TC) and a variable resistance element (RR); a word line (WL) connected to the cell transistor (TC); a word line (WL) connected to the cell transistor (TC); a data line (SL) connecting the cell transistor (TC) and the variable resistance element (RR) to each other; and a data line (BL) connecting the variable resistance element (RR) and the cell transistor (TC) to each other.

Nonvolatile semiconductor storage device having improved reading and writing speed characteristics

A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

Nonvolatile semiconductor memory device

A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.

Ground circuitry for semiconductor memory device

A nonvolatile semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged in a matrix; a reference bit line; a reference source line; at least one reference cell including first and second transistors serially connected between these lines; a reference word line connected to the gate of the first transistor; and a reference driver circuit configured to control the gate voltage of the second transistor.

A non-volatile semiconductor memory device includes a plurality of series-coupled fixed resistance elements, a plurality of reference cell transistors, and reference word lines coupled to gates of the reference cell transistors, a first reference data line coupled to one end of a resistance path in which a plurality of fixed resistance elements are arranged, and a second reference data line coupled in common to one ends of the reference cell transistors. The other end of each of the reference cell transistors is coupled to one of coupling points of the fixed resistance elements or the other end of the resistance path.

Non-volatile semiconductor memory device

Each of m word lines is connected to n memory cells in a corresponding one of rows of m&#xd7;n memory cells. Each of n bit lines is connected to m memory cells in a corresponding one of columns of m&#xd7;n memory cells, and each of n source lines is connected to m memory cells in a corresponding one of columns of m&#xd7;n memory cells. N first switching elements switch connection states between a reference node and the n bit lines, and n second switching elements switch connection states between the reference node and the n source lines. N third switching elements switch connection states between the write driver and the n bit lines, and n fourth switching elements switch connection states between the write driver and the n source lines.

A main bit line is disposed between a reference main bit line and core main bit lines. A selection transistor disposed between a sub bit line connected to a cell and the main bit line can switch between a conductive state and a non-conductive state independently of other selection transistors. A dummy main bit line can be set to ground potential by a shield grounding section, and can be used as a shield line of the reference main bit line.

In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.

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Osaka, Japan

Kazuyuki Kouno