Ricoh Company, Ltd.

Renesas Electronics Corporation

Nec Electronics Corporation

Kazuyuki Ito

Yoshihide Ohta

Takayuki Nishi

Hiroki Ishimitsu

Hiroshi Shirota

Katsuhiro Hoshi

Nobuhiro Shima

Keiichi Shimizu

Tadashi Saito

Hiroaki Murakami

Ryosuke Okuda

Masao Aramoto

An image forming apparatus includes a scanner to read an image on an original and an electric box disposed below the scanner and extended horizontally with respect to the scanner. The electric box includes an electric cabinet having a box shape and an electrical device disposed inside the electric cabinet.

Image forming apparatus

An image forming apparatus includes an outer cover, an interior device spaced apart from the outer cover, and an accommodating recess interposed between the outer cover and the interior device. The accommodating recess accommodates an arbitrary part of the image forming apparatus.

Image forming apparatus including an electronics container designed to permit an overall efficient structure

An image forming apparatus includes an electric wire and an electric box. The electric box extends substantially horizontally and includes a wire connector coupled to the electric wire. A body face exposes the wire connector. An outer cover covers the body face. The outer cover includes a slot and a wire accommodator. The slot is disposed opposite the wire connector to expose the wire connector to an outside of the image forming apparatus. The wire accommodator accommodates the electric wire.

Image forming apparatus including an outer cover and a subsidiary cover

If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuitincludes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FFprovided in a subsequent stage of a flip-flop FF, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FFand output of the flip-flop FFT. Test data tvand test data tvare input to the malfunction pre-detecting circuitin an operation test mode for testing operation of the malfunction pre-detecting circuit. The test data tvis input to the delay circuit DL. The comparator CMP compares the test data tvand output of the flip-flop FFT in the operation test mode.

Semiconductor device

This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.

Digital broadcasting receiving unit and digital broadcasting system

In a semiconductor device including active areas where transistors are formed and a field area for isolating the active areas from each other, the field area has a plurality of dummy areas where dummy gates are formed.

Growing community of inventors

Kanagawa, Japan

Kazuyuki Ito