Mitsubishi Denki Kabushiki Kaisha

Kazuyuki Ishikawa

Yukihiko Shimazu

Kouichi Ishimi

Toshiki Fujiyama

A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.

Clock delay circuitry producing clock delays less than the shortest delay element

An adder circuit includes a Manchester-carry-chain circuit which propagates a carry signal for each block consisting of plural bits, and a carry-look-ahead circuit which selects said carry signal in response to a carry propagation signal being generated by a full adder, and when the carry signal is not generated in the two consecutive blocks, an output from the Manchester-carry-chain circuit is selected by the carry-look-ahead circuit, so that the carry signal being inputted to the low-order block of the two blocks can be propagated as the carry signal to be outputted from the high-order block.

Growing community of inventors

Tokyo, Japan

Kazuyuki Ishikawa