Oki Electric Industry Co., Ltd.

Kazuyuki Inokuchi

Tadashi Saito

Masahisa Ikeya

Seiichi Takahashi

Shinichi Hoshi

Nobusuke Yamamoto

Nobumasa Higemoto

Yuko Itoh

Yoshiaki Sano

A semiconductor device fabrication process includes forming a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure having a lower portion that penetrates through the cap layer and reaches the Schottky layer, and having an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.

Semiconductor device and process of fabricating same

A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.

Integrated circuit and fabricating method and evaluating method of integrated circuit

A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.

Semiconductor device with Schottky layer

Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate

FET gate bias voltage application circuits and semiconductor apparatuses in which such a FET gate bias voltage application circuit is installed compensate for adverse effects caused by changes in the surrounding temperature. A temperature compensation FET is installed in a FET gate bias voltage application circuit in which a divided voltage is applied to the gate of a controlled FET from a first intermediate point of a resistance type potential dividing circuit to which a direct current voltage is applied. This temperature compensation FET becomes conductive at a gate voltage higher than the gate voltage of the controlled FET. A voltage divided at the first intermediate point is applied to the gate of this temperature compensation FET. The drain of this temperature compensation FET is connected to a second intermediate point at which the electric potential is higher than the electric potential at the first intermediate point. The source of this temperature compensation FET is grounded. This temperature compensation FET remains non-conductive when the gate-drain current of the controlled FET is at a low level. This temperature compensation FET becomes conductive when the gate-drain current of the controlled FET increases to a high level to cause a drain-source current to flow through this temperature compensation FET. As a result, the amount of voltage drop increases at a region in which the electric potential is higher than the electric potential at the second intermediate point of the resistance type potential dividing circuit. This causes the electric potentials at the first and second intermediate points, respectively, to be shifted in the negative direction.

Field effect transistor gate bias voltage application circuit and

Integrated circuit and fabricating method and evaluating method of

A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.

Solid-state antenna switch and field-effect transistor

In a method of making a semiconductor device, an active layer and a heavily doped cap layer are formed in turn on a semiconductor substrate, a first electrode is formed on the cap layer, a mask of a two-layer structure is formed on the cap layer, with the mask having an insulating film pattern having a non-inverted tapered opening, and a resist pattern having an inverted tapered opening and continuous with the non-inverted tapered opening, these openings being separated by a predetermined distance from the first electrode, and then a recess is formed, by performing an isotropic etching of the heavily doped layer exposed in the openings, with the recess having a bottom surface and a side wall surface rising from an edge of the bottom surface toward the upper edge with a constant radium off curvature. An oblique vapor deposition is then performed to form a second electrode to cover the bottom surface and the part of the side wall surface.

Compound semiconductor device and method of making it

A lower mask layer and a first resist layer are formed on a substrate. The first resister is exposed with the use of an exposure mask having a phase shifter. A part of the first resist layer corresponding to the edge of the phase shifter becomes an unexposed part so that an aperture in slit is formed in the first resist layer by developing. The first mask layer is etched through said first resist layer to form an aperture for forming a gate electrode. A second resist layer as an upper mask layer is formed over the lower mask layer. The second resist layer is exposed with the use of the same exposure mask, and is then developed. By setting the exposure strength to a value lower than an exposure strength for exposure to the first resist layer, a wider aperture is formed in the second resist layer. With the use of the lower mask layer having the narrower aperture and the upper mask layer having the wider upper mask layer, a T-shape electrode is formed.

Method of forming T-shaped electrode

After doping a conductive layer made of a semiconductive material with impurites, a conductive layer with a deep trap level is formed by low temperature annealing. For forming such a conductive layer with a deep level, lattice defects are introduced into a conventional conductive layer through ion implantation and after that, only stable lattice defects, that can work as deep levels, remain by annealing at low temperature.

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Tokyo, Japan

Kazuyuki Inokuchi