Fujitsu Corporation

Kazuyuki Iida

Yasuhiro Yamashita

Ryoji Yamada

Hiroshi Miura

Masato Ariyama

Masaharu Nishimura

Toshiyasu Sakata

Akira Katsumata

Tomohisa Suzuki

Mitsunobu Okano

Hiroyuki Orihara

Hirofumi Hamamura

Mitsuru Yasuda

Atsushi Yamane

Junko Taira

Minoru Yabumoto

Kiyoyuki Yoshida

Hiroichi Kuwahara

Kazufumi Iwahara

Naoki Murakami

Ryouji Yamada

Minako Kubota

Yumiko Katsuyama

In designing integrated circuits such as FPGAs, a design support environment including the quality of design data is improved and the design efficiency is improved. An integrated-circuit design support apparatus that supports designing of an integrated circuit having a plurality of pins is provided. The apparatus includes a processor (a central processing unit) that forms a pin layout matrix (a matrix sheet) by unifying pin layout information of the integrated circuit using a common format and arranging the pin layout information in coordinates. The processor creates an integrated-circuit design library from the pin layout matrix.

Apparatus, method and program for supporting designing of integrated circuit using a common format

A wiring device and wiring method suitable for designing LSIs or printed boards or the like. The wiring device includes a wiring pattern editing unit for editing wiring patterns; a noise analyzing unit for analyzing a noise occurring when a circuit is operated according to the wiring patterns edited by the wiring editing unit; and a noise occurring spot specifying unit for specifying a spot when noise occurs in the wiring pattern, based on the solution analyzed by the noise analyzing unit and the wiring pattern edited in the wiring pattern editing unit The man-hours of an operator can be reduced by interlocking the crosstalk noise analysis with the wiring pattern editing function and then by reducing the number of man-hours needed to correct a wiring pattern by an operator.

Wiring device and wiring method

This invention is directed to a method and apparatus to find out an optimum solution in automatic routing or automatic placement with certainty and at a high-speed to improve a routing rate, and to realize automatic routing in a high-density. To these end, a routing approach is selected in a conversational mode while routing efficiency is consulted to compose routing processing procedure so as to generate a routing program. Besides, component placement processing procedures designated according to placement control information are combined to generate the placement program. A straight line between component pins adjacent to each other is defined as a chord, a wave for maze method routing is generated from a start point toward an end point of a routing path and propagated between the chords adjacent to each other. Positions of the chords through which the wave has passed until reaching the end point from the start point are successively stored and the positions through which the wave has passed is traced back to the start point from the end point when the wave reaches the end point to decide a routing path of the routing pattern. The method and apparatus of this invention are applicable to routing design or component placement design of LSIs, multichip modules, printed circuit boards, etc.

Routing program generating method and apparatus therefor, placement

A wiring CAD apparatus wherein a situation of a noticed event can be identified at a moment on a screen. The wiring CAD apparatus comprises a searching timing detection section for detecting a new displaying processing/deletion processing timing as a searching timing for a non-wired pin, a non-wired pin searching section operable in response to the searching timing detected by said searching timing detection section for searching the non-wired pin, and a display data production section for producing display data in accordance with which the non-wired pin searched out by said non-wired pin searching section is to be displayed on a display section in a visually distinguishable condition from another already wired part pin. The display data produced by said display data production section is displayed on the display section under the control of a displaying control section. The wiring CAD apparatus can be applied to a CAD system with which wiring designing for an LSI, an MCM, a PWB or the like can be performed interactively.

Wiring CAD apparatus

A semiconductor circuit element device with an arrangement for testing the device including a plurality of first logic circuits provided in correspondence with internal line groups which are formed by grouping the internal lines into a plurality of groups, a plurality of internal lines belonging to a group in question constituting the input lines of the plurality of first logic circuits, for outputting an active output signal when all of the inputs represent active signals and outputting an inactive output signal when at least one of the inputs represents an inactive signal; and a second logic circuit constituted by one or more stages of circuit structures, for receiving the outputs of the first logic circuits and sending out an output signal such that the output signal in the case where all of the inputs are inactive output signals is different from the output signal in the case where at least one of the inputs is an active output signal.

Semiconductor circuit element device with arrangement for testing the

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Kawasaki, Japan

Kazuyuki Iida