Hitachi, Ltd.

Hitachi Communication Technologies, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Kazuyuki Hori

Shouhei Murakami

Yuji Ishida

Takashi Yano

Satoshi Tanaka

Kazuo Watanabe

Masumi Kasahara

Yukinori Akamine

Manabu Kawabe

May Suzuki

Ken Takei

Hiroshi Okabe

Shigenori Hayase

Masanori Taira

Yoshiaki Hasegawa

Toshiaki Kurokawa

Tomoya Uchiike

Hiroshi Kishida

Takahiro Chiba

Mikio Kuwahara

Masaru Kokubo

Kenji Sekine

Masamitsu Nishikido

Hideaki Arai

Yuuji Ishida

Keiichi Hirota

Norie Hara

Yoshitaka Imakado

Yasuyuki Magara

Qian He

Kenji Yanagi

Haruo Nakano

Tomonori Nomura

To satisfy the required SNR values for each system and/or each channel, a peak factor reduction device for reducing peak components included in a transmission signal, generates a cancellation signal to be multiplexed on the transmission signal, and the peak factor reduction device changes an amplitude of the generated cancellation signal according to a signal noise ratio required for the transmission signal and a power level of the transmission signal.

Peak factor reduction device and wireless transmitter

To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.

Orthogonality detector, and quadrature demodulator and sampling quadrature demodulator using detector thereof

Even if a receiver has a normal gain and a lowered intermodulation distortion characteristics, a fault detection is possible. A test signal transmitter sends a test signal having at least two frequencies to a radio receiver through a coupler. A digital signal processing section receives a signal which includes an IM3 component generated by the radio receiver and measures the electric power of fundamental wave components and the IM3 component. Then, the digital signal processing section calculates the gain of the radio receiver and IIP3, which is an index for intermodulation distortion characteristics, of the radio receiverfrom the calculated electric power. A base station control section determines whether the gain and IIP3 of the radio receiver fall in predetermined ranges to determine whether the radio receiver works normally or has a fault.

Radio base station and receiver fault diagnosis method

A matched filter and receiver is provided to delete the tap coefficients of a matched filter used in an OFDM receiver. In the matched filter and receiver, a transmitting signal is generated by using a symmetric series (Y) obtained from C[k]=exp[j*&#x3c0;*M/N*(k+0.5)^2], where X=[0, C[N/2], C[N/2+1], . . . , C[N&#x2212;1], 0, 0, . . . , 0, C[0], C[1], . . . , C[N/2&#x2212;1]], and Y=inverse FFT (X) as a base symbol. The matched filter, which detects the signal, reduces the number of multipliers by using the coefficient symmetric property.

Matched filter and receiver

The function of comparing power of a signal obtained by multiplying an input signal by an EVM target value and power of a peak suppression signal, and automatically adjusting a peak factor threshold value Vt in such a manner that the values of both power become equal to each other, is added to the peak factor reduction device. The peak factor reduction device is also added with the function of comparing instantaneous amplitude values of a signal Sout after a peak factor reduction and the peak factor threshold value Vt, and automatically calculating a peak detection width N so as to suppress the residual of each peak.

Peak factor reduction device and base station

There is a need for effectively compensating distortion when a predistortion transmitter is subject to not only a memory effect due to nonlinearity of an amplifier, but also a modulator's DC offset, IQ unbalance, or local quadrature error. A predistortor to be used is a polynomial predistortor including a polynomial basis generation portion and an inner product calculation portion. The polynomial basis generation portion delays a real part and an imaginary part of a complex input signal Sx=Ix+jQx for up to M samples to generate 2(M+1) signals, duplicately combines these signals to generate monomials having maximum degree N, and outputs, as a basis vector, all or part of the monomials depending or needs. The inner product calculation portion performs an inner product calculation using a coefficient vector, i.e., a set of complex numbers sized equally to the basis vector to find a polynomial value and outputs the value as a complex signal.

Digital predistortion transmitter

An object of this invention is to provide a method of designing a complex transfer function which can be realized in a passive RC complex filter at the same time while perfectly succeeding to features of a prototype lowpass characteristic. In this invention, as a first step, a prototype lowpass characteristic F(p) having a pole on a unit circle is designed. Next, as a second step, a bilinear variable transformation expressed by p=j(s&#x2212;j)/(s+j) is performed with respect to the prototype characteristic F(p) to derive a complex coefficient transfer function G(s). As a third step, a passive RC complex filter H(s) is designed based upon the complex coefficient transfer function G(s).

Method of designing passive RC complex filter of Hartley radio receiver

A wireless communication device including: a transmitter including two DA converter units which convert two digital signals into analog signals; a combiner which combines the analog signals; a distributor which extracts a portion of the combined signal as a feedback signal; an AD converter which converts the feedback signal; an oscillator unit which supplies clock signals to operate the DA converter units and the AD converter; a first separation unit which separates the feedback signal converted by the AD converter into two signals; and a comparator unit which compares at least one of the two digital signals that are obtained by separating the inputted digital signal, or, at least one of the two digital signals that are separately inputted, with the feedback signal separated by the first separation unit, wherein the oscillator unit controls the output clock signals based on a result of the comparison by the comparator unit.

Timing adjustment method for wireless communication apparatus

A peak factor reduction unit that never allow peak factor reproduction even when interpolation is done in a succeeding stage. The unit detects a local maximum value of amplitude components from an input complex signal and supplies a complex signal that passes a band limiting baseband filter and an interpolation filter to a correction signal generation unit for generating a correction signal used for peak factor reduction and reduces a peak factor of the input complex signal with use of the correction signal generated from an interpolated complex signal.

Peak factor reduction unit and baseband signal processing device

An OFDM modulator having a peak factor reduction function. The OFDM modulator has a peak factor reduction unit between an IFFT unit and a guard interval insertion unit thereof. The peak factor reduction unit converts a complex signal Xoutputted from the IFFT unit into a complex signal Xwith a reduced peak factor based on subcarrier map information. The peak factor reduction unit generates a peak factor reduction signal by a linear combination of complex exponential functions that correspond to subcarrier frequencies to be used for wave transmission, as bases. The peak factor reduction signal is derived by repetition of, for example, a weighted least squares method or convolution processing by a fast Fourier transform.

OFDM modulator

The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Phase locked loop circuit

Disclosed are a delay locked loop circuit capable of accurately extracting nonlinear distortion superimposed on an output of a digital predistortion type transmitter, the digital predistortion type transmitter, and a wireless base station using the same. The delay locked loop circuit outputting a smoothed signal to the variable delay element, in which delay control is implemented for checking distortion occurring to the output IQ signals due to the same passing through the analog circuit by means of the variable delay element. Either the first input IQ signals or the second input IQ signals are signals generated as a result of output IQ signals Io, Qo undergoing digital-to-analog conversion, and again undergoing analog-to-digital conversion after passing through an analog circuit. In particular, an IIR filter may be used for the variable delay element.

Delay locked loop circuit, digital predistortion type transmitter using same, and wireless base station

A &#x3a3;&#x394; transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90&#xb0;, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.

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Tokyo, Japan

Kazuyuki Hori