Nec Corporation

Mitsubishi Heavy Industries Limited

Japan Aerospace Exploration Agency

Kazuyuki Hirose

Daisuke Kobayashi

Daisuke Matsuura

Osamu Kawasaki

Kuniko Kikuta

Takanori Narita

Masahiro Kato

Kazuyoshi Ueno

Kuniko Miyakawa

Shigeru Ishii

Yoshiharu Mori

Masaki Kusano

Yuya Kakehashi

Taichi Ito

The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus () for compensating for radiation tolerance comprises: a voltage value acquisition unit () that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit () that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit () that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

Apparatus for compensating for radiation resistance of semiconductor memory, method therefor, and electronic circuit

A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

Semiconductor devices

An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.

Semiconductor device

A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier method is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.

Method for manufacturing a semiconductor device having fine contact hole

A method of burying a conductive metal into a contact hole formed in an insulation film formed over a silicon substrate. Within the contact hole a refractory metal silicide layer has been formed on the silicon substrate and a barrier metal layer has been formed on the refractory metal silicide layer and further a conductive metal film has been formed on the barrier metal layer. A top surface region of the conductive metal film is rapidly heated to a first temperature below a melting point of the conductive metal film and high enough so as to cause a semi-fluidization of only the top surface region of the conductive metal film so as to maintain an interface between the barrier metal layer and the conductive metal film at a second temperature which is lower than the first temperature and low enough so as to prevent any chemical reaction between the barrier metal layer and the conductive metal film and also maintain the refractory metal silicide layer and the silicon substrate to have temperatures lower than the second temperature so as to prevent silicon from being diffused through the barrier metal layer into the conductive metal film.

Method of burying a contact hole with a metal for forming multilevel

A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier metal is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.

Semiconductor device having fine contact hole with high aspect ratio

The method of manufacturing the metal-semiconductor junction in accordance with the present invention includes the step of forming a 2.times.2 surface superstructure in an ultrahigh vacuum by removing an oxide layer by means of a heat cleaning at temperatures not lower than 600.degree. C. while irradiating a (111) A or (111) B surface of a zincblende-type III-V compound semiconductor substrate with a beam of a group V element, the step of cooling the substrate down to room temperature while maintaining the surface superstructure and the step of depositing a metal on the surface.

Growing community of inventors

Tokyo, Japan

Kazuyuki Hirose