Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Nissan Motor Company Limited

Kioxia Corporation

Sony Corporation

Nuflare Technology, Inc.

Kabushiki Kaihsa Toshiba

Kazuyuki Higashi

Noriaki Matsunaga

Naofumi Nakamura

Ryota Katsumata

Akihiro Kajita

Atsuko Sakata

Makoto Wada

Hisashi Kaneko

Junichi Wada

Hideki Shibata

Masayoshi Tagami

Jun Iijima

Masaaki Hatano

Tsuneo Uenaka

Masaki Yamada

Tomio Katata

Seiichi Omoto

Masahiko Hasunuma

Kazumichi Tsumura

Soichi Yamashita

Kazuya Kinoshita

Tetsuo Matsuda

Yoshiaki Shimooka

Katsuya Okumura

Tadashi Iijima

Mitsuyoshi Endo

Kenji Yoshida

Takeshi Nishioka

Tadashi Matsuno

Minakshisundaran Balasubramanian Anand

Motoya Okazaki

Kengo Uchida

Takashi Shirono

Takeshi Fujimaki

Hitomi Yamaguchi

Tamao Takase

Yoshiaki Fukuzumi

Yoshiaki Sugizaki

Fumitaka Arai

Hiroshi Matsumoto

Yoshinori Sato

Shinya Watanabe

Takeshi Ishizaki

Tadashi Iguchi

Toshiaki Hasegawa

Hiroshi Toyoda

Hirokazu Ezawa

Hideshi Miyajima

Satoshi Wakatsuki

Hirofumi Morita

Kiyotaka Tabuchi

Gaku Sudo

Masato Endo

Ippei Kume

Toru Matsuda

Tatsuo Migita

Akiko Nomachi

Kenro Nakamura

Yoshikuni Goshima

Keiji Fujita

Koji Ogiso

Taku Kamoto

Kanae Uchida

Nobutaka Watanabe

Shinsuke Yonetani

Mika Fujii

Kei Obara

Miyoko Shimada

According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Semiconductor memory

A semiconductor device according to an embodiment includes: a substrate including a plurality of through holes provided at predetermined intervals along a first direction in a substrate surface and along a second direction intersecting the first direction in the substrate surface; an insulating layer provided on the substrate, the insulating layer being penetrated by the through holes; a plurality of first electrodes provided on the insulating layer, the first electrodes being adjacent to the respective through holes in the first direction; a plurality of second electrodes provided on the insulating layer, the second electrodes being adjacent to the respective through holes in the first direction, the second electrodes being provided to face the first electrodes, the second electrodes being held at a predetermined potential; and a wiring layer provided on the insulating layer, the wiring layer electrically connecting the adjacent second electrodes.

Semiconductor device, multi-charged-particle beam writing apparatus, and multi-charged-particle beam exposure apparatus

According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.

Semiconductor device and semiconductor device manufacturing method

A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

Semiconductor memory device

According to one embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes three steps of a providing step, a bonding step, and a thinning step. In the providing step, a mitigation layer that mitigates warping of the device substrate being thinned by grinding is provided on the supporting substrate. In the bonding step, the device substrate is bonded to the supporting substrate on which the mitigation layer is provided. In the thinning step, the device substrate supported by the supporting substrate is thinned by grinding.

Method of bonding supporting substrate with device substrate for fabricating semiconductor device

A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate. The insulating film covers a semiconductor element. The conductive film penetrates the semiconductor substrate across from the first surface to a second surface opposite to the first surface. On the second surface, a trench continuously or intermittently exists across from a first end part side of the second surface to a second end part side thereof.

Semiconductor device and manufacturing method thereof

According to one embodiment, a method of manufacturing a semiconductor device comprises forming through holes extending through a semiconductor substrate in a thickness direction to integrated circuits in chip areas, and forming a first mark opening and second mark openings in a dicing line. The method detects the first mark opening based on positions of the second mark openings. Then, the method performs alignment of exposure positions based on the position of the first mark opening to perform photolithography, thereby forming a resist pattern on the back side of the semiconductor substrate.

Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer

A semiconductor device including a semiconductor substrate having a first surface and a second surface, the first surface being configured for formation of a semiconductor element; a through hole extending through the semiconductor substrate; and a through electrode disposed in the through hole. The through electrode includes an insulating film disposed along a sidewall of the through hole, a conductive layer comprising a first material disposed along the insulating film, and an electrode layer comprising a second material filled inside the through hole over the conductive layer. The first material is softer than the second material. The second material has a melting point higher than a melting point of the first material. The electrode layer includes a void portion being closed near the second surface of the semiconductor substrate.

Semiconductor device

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

Semiconductor device and method of fabricating the same

According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.

Semiconductor device manufacturing method and manufacturing apparatus

Growing community of inventors

Yokohama, Japan

Kazuyuki Higashi