Nec Corporation

Nec Electronics Corporation

Renesas Electronics Corporation

Waseda University

Kazuyoshi Ueno

Toshiyuki Takewaki

Yoshihisa Matsubara

Takashi Ishigami

Tetsuya Osaka

Makoto Sekine

Tetsuya Homma

Manabu Iguchi

Kazumi Sugai

Shuichi Saito

Nobukazu Ito

Naoyoshi Kawahara

Kazuyuki Hirose

Hidekazu Okabayashi

Tetsuya Kurokawa

Akiko Fujii

Ryuji Tomita

Nao Takano

A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer and an insulating interlayer portion made of SiO. The method comprises the steps of treating, with a silane compound, a SiOsurface of the insulating interlayer portion on which the diffusion layer is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. A capping layer may be formed on the wiring layer by electroless plating. Consequently, a diffusion prevention layer having good adhesive properties can be formed through a simple wet process, and, the wiring layer can directly be formed on this diffusion prevention layer by a wet process. The capping layer can also be directly formed on the wiring layer by electroless plating.

ULSI wiring and method of manufacturing the same

A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.

Semiconductor device with improved stress migration resistance and manufacturing process therefor

In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

Method of forming a semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thicknesses formed thereon

The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S); forming a barrier metal layer on the whole surface of the insulating film (S); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S); and flattening the cap metal layer by polishing (S).

Semiconductor device and method of manufacturing the same

A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.

Semiconductor device manufacturing apparatus and semiconductor device manufacturing method

A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such that the trench is filled in with the metal layer; (D) forming the interconnection by removing an excess metal layer outside the trench; (E) modifying a surface of the insulating film to form a modified layer on the insulating film; and (F) forming a metal film selectively on the interconnection by using plating solution after the (E) modifying process.

Method of manufacturing semiconductor device

Semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thickness formed thereon, and method for manufacturing the same

A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film () and a copper containing metallic film () can be formed within an insulating film (). An interlayer insulating film (orand) can be formed thereon. An upper layer wiring made from a barrier metal film (orand) and a copper containing metallic film (orand) is formed within the interlayer insulating film (orand). A silver containing metallic protective film (and) can be formed on surfaces of the lower layer wiring and upper layer wiring.

Semiconductor device

Semiconductor device and manufacturing process therefor as well as plating solution

A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.

Semiconductor device with guard ring for preventing water from entering circuit region from outside

A semiconductor device includes a lower wiring layer, a first insulating layer formed on the lower wiring layer and having a via hole with a width, a via mask layer formed on the first insulating layer and having an opening with a width larger than the width of the via hole, a second insulating layer formed on the via mask layer and having an upper wiring, groove whose width coincides with the width of the via hole, a via contact structure buried in the via hole, and an upper wiring layer buried in the upper wiring groove.

Semiconductor device including dual-damascene structure and method for manufacturing the same

The manufacturing method of a semiconductor device includes a step of forming a lower wiring on a semiconductor substrate, a step of forming a layer insulating film on the lower wiring, a step of forming an opening that exposes the lower wiring by removing a part of the layer insulating film, a step of forming a barrier film in the opening and a step of forming an upper wiring in the opening, where the lower wiring and the upper wiring are copper including wirings composed of copper or a copper alloy, the barrier film covers the bottom face and the side face of the opening, and the barrier film on the bottom face of the opening is formed so as to have its thickness to be less than twice the diffusion length of the copper atoms in the barrier film.

Manufacturing method of a semiconductor device

The present invention relates to a copper interconnection comprising a copper or copper alloy layer, wherein at least 50% of crystal grains of copper or a copper alloy form twins. A copper interconnection of the present invention is, therefore, highly reliable, and, a production cost thereof is low.

Growing community of inventors

Tokyo, Japan

Kazuyoshi Ueno