Kabushiki Kaisha Toshiba

Vlsi Technology Research Association

Tokyo Shibaura Denki Kabushiki Kaisha

Kazuyoshi Shinada

Masaki Sato

Naoki Hanada

Takahide Mizutani

Masayuki Yoshida

Yasoji Suzuki

Yuuichi Mikata

Isao Abe

Satoshi Shinozaki

Toshiro Usami

Osamu Matsumoto

Tadashi Maruyama

Tomohisa Shigematsu

Hiroyoshi Murata

Ichiro Kobayashi

Teruo Uemura

Akira Kimitsuka

Tatsuo Mori

There is provided a method of manufacturing a semiconductor device including a nonvolatile memory including forming an element isolation area surrounding an element area in a semiconductor substrate doped with a first type conductive impurity, forming a gate insulating film on the element area, forming selectively a cap film on the gate insulating film, burying selectively with a mask film surrounding the cap film on the gate insulating film, forming a tunnel window by removing selectively the cap film, forming an impurity diffusion layer in a surface region of the semiconductor substrate underneath the gate insulating film by introducing a second type conductive impurity using the mask film as a mask, removing the gate insulating film in the tunnel window, forming a tunnel insulating film in the tunnel window, forming a floating gate electrode film, an inter-gate electrode film, and a control gate electrode film on the tunnel insulating film, and forming a source-drain in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the control gate electrode film by introducing the second type conductive impurity into the surface region using the control gate electrode film as a mask.

Method of manufacturing semiconductor device including nonvolatile memory

A testing pad is connected to an EEPROM through a wiring layer of a security circuit and a test circuit, while a testing pad is connected to the EEPROM through a wiring different from the wiring layer and the test circuit. A polysilicon pattern is connected to the wiring layer, and an n-type diffusion region is connected to the wiring. A tunnel insulation film having a thickness of about 100 .ANG. is formed between the polysilicon pattern and the n-type diffusion region. After a test for the function and stored information of the EEPROM is completed, a voltage, which is not lower than a predetermined voltage applied during the test, is applied between the testing pads to break the tunnel insulation film, thereby making the polysilicon pattern and n-type diffusion region conductive.

Semiconductor device having a security circuit for preventing illegal

An E.sup.2 PROM and an EPROM are formed on the same substrate. An E.sup.2 PROM memory cell has a floating gate and a control gate. A tunnel insulating film is formed between the floating gate and source/drain regions, thereby constituting a memory cell of an 'FLOTOX' type. An EPROM memory cell has a floating gate and a control gate, thus constituting a memory cell of an 'SAMOS' type.

Semiconductor device having E.sup.2 PROM and EPROM in one chip

A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

Method for manufacturing semiconductor device having a non-volatile

A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Nonvolatile semiconductor memory device with a double gate structure

A method for manufacturing a CMOS type semiconductor device is shown which includes the following steps. A first and a second conductive diffusion region are formed in a well region and a semiconductor substrate, respectively, and a gate electrode is formed thereon. An insulation layer is formed on the semiconductor substrate and the well region. A contact hole is opened by selectively removing the insulation layer corresponding to the first and the second conductive diffusion regions. At least one metal layer selected from a group consisting of metal and metal silicide having a high melting point is formed on an exposed surface of the first and the second conductive diffusion regions. The semiconductor substrate is heated to melt at least part of the insulation layer and form a tapered portion. A wiring layer is formed on the contact hole. This method prevents the contact resistance from increasing, the impurity of one region from diffusing into the other impurity regions, the impurity of the impurity regions from decreasing, and improves the reliability of the wiring layer by forming a tapered contact hole. These advantages permit high component density by miniaturizing the device.

Method for manufacturing a complementary MOS type semiconductor device

A semiconductor device is manufactured by forming a first insulating film on a surface of a semiconductor substrate of a first conductivity type, and a first nonmonocrystalline silicon film is formed on the first insulating film. A second insulating film is deposited on the first nonmonocrystalline silicon film by CVD, sputtering or molecular beam method. An impurity is then ion-implanted in the first nonmonocrystalline silicon film through the second insulating film. The second insulating film is then removed to expose the surface of the first nonmonocrystalline silicon film doped with the impurity, and a thermal oxide film is formed on the exposed portion of the first nonmonocrystalline silicon film. Subsequently, a second nonmonocrystalline silicon film is formed on the thermal oxide film, and a third insulating film is formed on the second nonmonocrystalline silicon film.

Method of manufacturing SiO.sub.2 -Si interface for floating gate

A method of producing a MOS transistor of LDD structure with p(n) type pockets. A doped oxide film in which impurities such as phosphorus and impurities such as arsenic are doped is formed on a semiconductor substrate, and a nitride film is formed in regions where p type pockets are formed on the both sides of a gate electrode. By implementing heat treatment in the atmosphere of oxygen, the portion below the nitride film is placed in the condition where it is equivalent when heat treated in the atmosphere of nitrogen whereby a p type impurity region and an n.sup.- type impurity region are formed. The region except for that below the nitride film is heat treated in the atmosphere of oxygen to form an n.sup.+ type impurity region. Further, with the gate electrode as a mask, n.sup.- type impurity region and p type impurity region are formed, thereafter selectively growing a film on the side walls of the gate electrode to form an n.sup.+ type impurity region with the gate electrode and the film as masks, thus producing a MOS transistor.

Method of producing semiconductor device

This invention provides a method for manufacturing a bipolar transistor which comprises steps of selectively forming in the surface of a semiconductor substrate an embedded layer of a conductivity type opposite to that of the substrate, covering the substrate with an insulating layer doped, at the surface thereof with an impurity in the superficial region thereof, removing by etching the insulating layer to form an opening portion through which part of the embedded layer is exposed, simultaneously forming by epitaxial growth a single-crystal semiconductor layer of the same conductivity type as that of the embedded layer on the embedded layer at the opening portion and a polycrystalline semiconductor layer on the insulating layer, diffusing by heating the impurity in the insulating layer into the polycrystalline semiconductor layer to provide a conductivity type opposite to that of the single-crystal semiconductor layer, and successively forming an internal base region and an emitter region in the single-crystal semiconductor layer. The invention also provided a bipolar transistor manufactured by the aforementioned method.

Method of making a bipolar transistor

Disclosed is a method for manufacturing a semiconductor device. In this method an oxidation-resistive insulating film is formed on a silicon body of a one conductivity type. A first impurity region of the opposite conductivity type is selectively formed in said semiconductor body before or after said insulating film is formed. Part of said insulating film which corresponds to part of said first impurity region is etched and exposed portions of said silicon body are etched by isotropic etching to a predetermined depth, using said oxidation-resistive insulating film as a mask. An impurity of the opposite conductivity type is doped into said first impurity region, using said insulating film as a mask, so that a second impurity region of the opposite conductivity type whose concentration is higher than a concentration of said first impurity region is formed in said first impurity region and said silicon body. Thermal oxidation is performed using said insulating film as a mask, so that a continuous oxide film is formed to cover exposed portions of said first impurity region, said second impurity region and said semiconductor body. And a third impurity region of the one conductivity type is formed in said first impurity region which is exposed, after part of said insulating film on said first impurity region is etched. The method of this invention is advantageous for manufacture of a bipolar integrated circuit of high switching operation, high integration density and high reliability.

Method for manufacturing semiconductor device utilizing selective

A method of manufacturing a semiconductor device comprising a step of forming a desired opening in an insulating film formed on a single-crystalline semiconductor substrate, a step of forming an impurity-doped amorphous or polycrystalline semiconductor layer to cover the surface of said insulating film and the exposed surface of said semiconductor substrate in said opening, and a step of irradiating said semiconductor layer with a laser beam to let a portion of said semiconductor layer on said insulating film be polycrystallized or remain polycrystalline and let a portion of said semiconductor layer on said semiconductor substrate be single-crystallized to form a junction between said single-crystallized semiconductor layer portion and said semiconductor substrate.

Method of manufacturing semiconductor device using laser beam

A method for manufacturing a semiconductor device having a Schottky junction which comprises a process for burying first and second regions of a second conductivity type spaced from each other in a semiconductor body of a first conductivity type, a process for locally disposing a first interconnection layer made of a metal on a surface region of the semiconductor body facing the first region, a process for forming an insulating film on the surface of the first interconnection layer by subjecting the surface to anodic oxidation, a process for ion-implanting an impurity of the second conductivity type into the semiconductor body except a portion thereof under the first interconnection layer at such an energy level that the impurity may reach the first and second regions, a process for activating the ion-implanted layer by applying a laser beam thereto, and a process for forming a second interconnection layer connected with the activated layer by covering the whole surface of the semiconductor body with a metal and patterning the metal.

Growing community of inventors

Yokohama, Japan

Kazuyoshi Shinada