Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Mitsubishi Denki Kabushiki Kaisha

Other

Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Sugatsune Kogyo Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Vsli Engineering Corp.

Kazuyoshi Oshima

Takashi Yamazaki

Tetsurou Matsumoto

Hiroshi Kikuchi

Asao Nishimura

Kunihiko Nishi

Kunihiro Tsubosaki

Takashi Yokoyama

Gen Murakami

Makoto Kitano

Akihiro Yaguchi

Akio Hasebe

Hiroshi Hozoji

Masahiro Ichitani

Aizo Kaneda

Shozo Nakamura

Junichi Saeki

Isamu Yoshida

Sueo Kawai

Hiroyoshi Kokaku

Noriyuki Kinjo

Masatsugu Ogata

Masanori Segawa

Syuuji Eguchi

Yasuhiro Kasama

Kazuhiko Kajigaya

Kazuyuki Miyazawa

Shinji Udo

Masashi Horiguchi

Ryoichi Hori

Jun Etoh

Tetsuro Matsumoto

Eiji Miyamoto

Manabu Tsunozaki

Akira Endo

Yuji Sakai

Hiroshi Yoshioka

Yasunori Yamaguchi

Makoto Morino

Shinichi Ikenaga

Mitsuhiro Takano

Sinichi Miyatake

Jiro Sawada

Atsushi Kumata

Hirokazu Saito

Ichiro Anjo

Ichiro Anjoh

Hideaki Yamanaka

Hiroaki Kotani

Munenori Tsuzuki

Hirotaka Saito

Toshihiro Tanaka

Masayuki M Nakamura

Tetsu Udagawa

Hirotoshi Yamada

Katsutaka Kimura

Tatsuya Ishii

Hitoshi Miwa

Masataka Kato

Atsushi Nozoe

Tetsuya Tsujikawa

Yoshinori Sakamoto

Kiyoo Itoh

Takayuki Kawahara

Masakazu Aoki

Hiroyuki Uchiyama

Yasushi Takahashi

Toshio Sasaki

Atsushi Ohba

Tsugio Takahashi

Osamu Tsuchiya

Yoshifumi Kawamoto

Harufusa Kondoh

Hisashi Nakamura

Masamichi Ishihara

Kozo Watanabe

Hidetoshi Iwai

Atsushi Hiraiwa

Hiromi Notani

Michitaro Kanamitsu

Toshiyuki Sakuta

Yasuhiro Nakamura

Hiroshi Otori

Takashi Nishida

Masaya Suzuki

Tadashi Iijima

Kiyonori Ohyu

Shigeru Tanaka

Hiromi Matsuura

Kyoko Ishii

Toshio Maeda

Ken Shinmura

Hideki Ogasawara

Mitsuru Sugiura

Takayuki Yoshitake

Kiichi Manita

Shin'ichi Ikenaga

Osamu Sakai

Jun Sugasawara

Masanori Tazunoki

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Nonvolatile memory device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the &ldquo;Lead-On-Chip&rdquo; or &ldquo;Chip-On-Lead&rdquo; structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data read time through parasitic capacitance in the data lines to other data lines, switches (Qt,and Qt,&prime;) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.

Semiconductor memory device, nonvolatile semiconductor memory device, and their data reading method

Growing community of inventors

Ohme, Japan

Kazuyoshi Oshima