Kabushiki Kaisha Toshiba

Kazuyoshi Kohno

Atsushi Masuda

Yutaka Ota

Atsushi Mizuno

Ryuichiro Ohyama

Hironori Uetani

Takeshi Kitahara

Masatoshi Sekine

Hiroaki Nishi

Masami Aihara

Tsutomu Takei

A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.

Program segment searching for extension instruction determination to design a processor that meets performance goal

A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions

A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S); a test vector generation data preparation step of preparing data required for generating test vectors (S); and a test vector generation step of generating test vectors by the use of said data (S).

Automatic test vector generation method, test method making use of the test vectors as automatically generated, chip manufacturing method and automatic test vector generation program

A technique for automatically generating test vectors comprises an ISA specification analysis step of analyzing specifications of an instruction set architecture (ISA) of a processor (S ); a test vector generation data preparation step of preparing data required for generating test vectors (S ); and a test vector generation step of generating test vectors by the use of said data (S ).

Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.

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Kawasaki, Japan

Kazuyoshi Kohno