Fujitsu Corporation

Fujitsu Vlsi Limited

Kazuyoshi Kikuta

Masaru Sawada

Manabu Nakano

Hiroko Murakami

A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.

Semiconductor integrated circuit device

A/D with digital PLL

This invention relates to a method and apparatus for reading out a synchronizing signal recorded in a data portion of each of a number of sectors stored in a recording medium such as an optical disc, a write-in-once type magneto-optical disc and so on. Even when detection of a synchronizing a signal has failed, the succeeding re-synchronizing signal can be detected reliably so that, although a first one divided unit portion of data is dropped out, data following the re-synchronizing signal can be read out positively, thus reducing data read error rate.

Growing community of inventors

Kasugai, Japan

Kazuyoshi Kikuta