Cypress Semiconductor Corporation

Fujitsu Semiconductor Limited

Kazuyoshi Futamura

Koji Okada

Kazuhiro Tomita

Hiroyuki Matsunami

A device includes a master delay-lock loop (DLL) having a phase frequency detector connected in series with a charge pump that is to generate a control voltage. A slave DLL is coupled to the master DLL and has a delay line including a buffer to receive a slave clock and a series of delay cells coupled between the buffer and an output terminal that is to output a delay clock, the series of delay cells variably controlled by the control voltage. The master DLL and the slave DLL are powered by a power supply that experiences undershoot or overshoot in response to a load transient. A dummy load is coupled between the delay line of the slave DLL and an output of the power supply, the dummy load including an exclusive OR gate that receives, as inputs, a first output of the buffer and the delay clock.

Reducing delay-lock loop delay fluctuation

A DC-DC converter includes a first amplifier that amplifies a first difference between a first reference voltage and a feedback voltage corresponding to an output voltage, a second amplifier that amplifies a second difference between the first reference voltage and an integrated value of the feedback voltage, and a controller that controls a switching circuit to change the output voltage when the first difference reaches the second different.

DC-DC converter, control circuit, and power supply control method

A power supply device including a converter having a switch circuit to which an input voltage is supplied and a coil coupled between the switch circuit and an output end from which an output voltage is output; and a control circuit comparing between a feedback voltage and a reference voltage, and on/off controls the switch circuit according to a comparison result; wherein, the control circuit includes a current gradient detection circuit performs detection of a gradient of a coil current flows thorough the coil during an off period of the switch circuit and generates a slope voltage according to a result of the detection; and an adder circuit performs one of generating the feedback voltage by adding the slope voltage to a voltage according to the output voltage and generating the reference voltage by adding the slope voltage to a standard voltage that is set according to the output voltage.

Growing community of inventors

Kasugai, Japan

Kazuyoshi Futamura