Nippon Telegraph and Telephone Public Corporation

Kazuyoshi Asai

Katsuhiko Kurumada

Yasunobu Ishii

A field effect transistor device is constituted by a semiinsulating substrate consisting of a compound semiconductor, an N type semiconductor layer formed on the substrate, a plurality of P type semiconductor gate regions aligned along a straight line and extending through the semiconductor layer to reach the substrate, source and drain electrodes disposed on the semiconductor layer on the opposite sides of the drain regions, a gate electrode having an ohmic contact with the gate regions and having a Schottky contact with the semiconductor layer interposed between the gate regions. Two gate regions on the opposite ends of the array are in contact with the boundary region of the transistor. The field effect transistor device is useful for fabricating an integrated circuit and consumes less electric power. Further it reduces dispersion in the gate pinch off voltage and can be prepared at a high yield.

Field effect transistor with combination Schottky-junction gate

In a field effect semiconductor device comprising a semi-insulator layer composed of a semiconductor material, an N conductivity type active layer made of the same semiconductor material and acting as a channel, spaced cathode and anode electrodes formed on the active layer, the cathode electrode being in ohmic contact with the active layer, and means for applying drive voltage across the cathode and anode electrodes for varying the electrons flowing through the active layer so as to vary output current, a P conductive region is provided beneath the anode electrode and extending through the active layer toward to or penetrating into the semiconductor layer.

Field effects semiconductor devices

A method of manufacturing a field effect transistor uses a semiinsulating substrate consisting of a compound semiconductor, and an N type semiconductor layer formed on the substrate. The method comprises the steps of implanting ions of a P type impurity from the main surface of said semiconductor layer to form at least two P type gate regions which extend from the main surface to substantially reach said substrate and are disposed with a predetermined interval, and sintering metallic layers on the gate regions in ohmic contact and on opposite sides of the semiconductor layers with said semiconductor gate regions being interposed therebetween to form a gate, a source and a drain electrodes. Said implantation step further comprises a step of positioning at least two of said gate regions such that said gate regions come in contact with the boundary region of the transistor to be constructed. The method of manufacturing the field effect transistor is useful for fabricating the field effect transistor at a high yield which is suitable to assemble an integrated circuit.

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Iruma, Japan

Kazuyoshi Asai