Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubushi Denki Kabushiki Kaisha

Kazuyasu Fujishima

Yoshio Matsuda

Hideto Hidaka

Kazutami Arimoto

Masaki Tsukude

Tsukasa Ooishi

Mikio Asakura

Hideshi Miyatake

Masaki Kumanoya

Katsumi Dosaka

Hideyuki Ozaki

Shigeki Tomishima

Kazuhiro Shimotori

Tsutomu Yoshihara

Yasuhiro Konishi

Kazutoshi Hirayama

Masahiro Shimizu

Tadashi Nishimura

Katsuhiro Tsukamoto

Tadato Yamagata

Takahiro Tsuruda

Hiroshi Kimura

Shigehiro Kuge

Yasumasa Nishimura

Shuji Murakami

Yasushi Terada

Masanori Hayashikoshi

Michihiro Yamada

Katsuhiro Suma

Shinji Kawai

Mikio Deguchi

Takao Nakano

Kouichi Nagasawa

Masahiro Tomisato

Tsukasa Oishi

Charles A Hart

Tsukasa Ohishi

Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss&#x2032;.

Semiconductor memory device capable of overcoming refresh disturb

Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss&prime;, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss&prime;.

Semiconductor memory device

On transistors P , P , N and N constituting an NAND gate, a interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al and Al are stacked. A local line LL for connecting transistors P , P , N and N to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL&prime; for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al , and power supply lines VL and VL&prime; for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al . As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al , the degree of freedom in layout can be improved and the layout area can be reduced.

Semiconductor integrated circuit

A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Semiconductor memory device for simple cache system

In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

Method of manufacturing semiconductor device

A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Semiconductor memory device with redundancy circuit

Semiconductor device and method of manufacturing the same

On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

Semiconductor device comprising a plurality of interconnection patterns

Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

Semiconductor memory device and data transferring structure and method

Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.

Hierarchical bit line arrangement in a semiconductor memory

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Hyogo, Japan

Kazuyasu Fujishima