Matsushita Electric Industrial Co., Ltd.

Kazuya Uyeda

Masanori Hamada

Kenta Sokawa

Hideaki Yamauchi

Takuji Okamoto

Takashi Yamaguchi

Kazuo Kobo

Robert Ho

A contour restoration apparatus has a plurality of delay circuits connected in series. Maximum and minimum value detection circuits detect maximum and minimum values among an input video signal and output signals of the delay circuits. A mean value circuit is used to calculate a mean value of the of the maximum and minimum values. The mean value is subtracted from a delayed signal having a delay time of one-half of a delay time obtained from all the delay circuits. An adder is used to add the result of the subtraction to the delayed signal. A non-linear processing circuit processes the output of said adder and the maximum and minimum values. The non-linear circuit outputs the output signal of the adder, if the output signal of said adder is between the maximum value and the minimum value. A contour extraction circuit multiplies a signal located centrally among the input video signal, the output signals and the signals located before and after the input signal with a predetermined coefficient. An adder adds the multiplied signals. Another adder adds the result of multiplied signal and the centrally located signal. A contour amplitude circuit detects a difference between the maximum and minimum values and outputs a coefficient determined according to the difference detected. A mixer mixes the output of the non-linear processing circuit and the output of the another adder.

Contour restoration apparatus

A contour restoration circuit comprises an input terminal, a plural of delay circuits connected to the input terminal in series, a maximum value detection circuit, a minimum value detection circuit, a mean value calculating the mean value from the maximum and minimum values, a subtractor for subtracting the mean value from the input video signal, a gain controller for the subtracted signal, an adder for adding the gain controlled signal to the input video signal and an output terminal.

A waveform equalizing system includes a clock reproducing phase locked loop circuit for reproducing a clock signal from a television signal; a transversal filter; a first selector circuit for alternatively passing the television signal or an output of a first memory to the transversal filter; a CPU for extracting reference signals contained in the television signal from the input and output of the transversal filter through two second memories respectively and for performing a synchronous addition of the same; the first memory for storing a reference signal processed by the synchronous addition; and a second selector circuit for alternatively delivering the television signal or an output of the transversal filter in response to a control signal from the CPU. The CPU is arranged for calculating a phase difference between the clock signal of the clock reproducing circuit and its ideal form from the reference signal processed by the synchronous addition and controlling a clock signal phase of the clock reproducing phase locked loop circuit to correct the phase difference.

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Suita, Japan

Kazuya Uyeda