Fujitsu Corporation

Fujitsu Microelectronics Limited

Kazuya Taniguchi

Toshiyuki Nishii

Hiromichi Mizuno

Yukisato Miyazaki

Osamu Matsuura

Kunihiro Ohara

Hiroshi Naritomi

Masayuki Takeshige

Kazuo Ohno

Sumitaka Hibino

Hayato Isobe

Tsutomu Terazawa

Teruyoshi Kondo

The present invention provides an input/output device capable of bringing a per-unit input/output circuit into a simple configuration without impairing reliability even when logic levels opposite in polarity are outputted between input/output devices made conductive to the outside. The input/output device is equipped with one reference port Pk selected from a port group which inputs and outputs signals, target ports Pt selected from other than the reference port of the port group, and a conduction detector which detects that conduction is made between input/output terminals for the reference port Pk and the target ports Pt.

Input-output device and control method thereof

A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.

Semiconductor device including voltage level conversion output circuit

There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.

Data buffer circuit, interface circuit and control method therefor

A microcontroller, connected to a memory which stores instructions and data, includes an instruction execution unit for reading instructions and data from the memory and processing the read instructions and a prefetch circuit unit that receives the instructions and data read from the memory and detects pseudo instructions included in the instructions and data. A pseudo instruction precedes a branch instruction and indicates the existence of the branch instruction and the branch to address. The prefetch circuit unit includes a prefetch buffer connected between the instruction execution unit and the memory for temporarily storing instructions and data being transferred from the memory to the instruction execution unit and a pseudo instruction buffer for temporarily storing instructions and data located at the address of the branch instruction which follows the pseudo instruction. Then, if the branch is taken, the branch to instructions have been prefetched and are immediately available to the instruction execution unit by way of the pseudo instruction buffer.

Microcontroller having prefetch function

A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.

Method and apparatus for compactly storing instruction codes

Growing community of inventors

Kasugai, Japan

Kazuya Taniguchi