Fujitsu Corporation

Kazuya Takaku

Kenji Suzuki

Hiroshi Nakayama

Hidekazu Osano

Masanori Higeta

Yasufumi Honda

Hideyuki Sakamaki

Fumitake Sugano

An information processing apparatus includes a processor, a plurality of memories, and a memory control circuitry coupled to the processor and the plurality of memories. The memory control circuitry controls access to the plurality of memories. The memory control circuitry includes a plurality of memory control circuits corresponding respectively to the plurality of memories, and a request distribution circuit that outputs the memory access request and a setting change request from the processor to one of the plurality of memory control circuits. Each of the plurality of memory control circuits includes an address translation control circuit that replaces bits of an address included in the memory access request based on allocation of bits changed based on the setting change request, and an access control circuit.

Information processing apparatus, memory control circuitry, and control method of information processing apparatus

A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Memory controller and information processing apparatus

To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the ranks and address signal lines via which to flow address signals specifying addresses on the rank, and a control unit transmitting the signal for selecting the rank via part of the address signal line and via the selection signal line.

Memory control device

A memory system connected to another apparatus via a data crossbar, has a first memory, a second memory that forms a dual configuration together with the first memory, a first memory controller that transmits or receives data to be written into the first memory or data read out from the first memory to or from the other apparatus, a second memory controller that transmits or receives data to be written into the second memory or data read out from the second memory to or from the other apparatus, and a system controller that instructs the first memory controller and the second memory controller to read out, from the first memory and the second memory, data requested to be read out by the other apparatus if the system controller detects that any one of the first data crossbar and the second data crossbar being not capable of transmitting or receiving data.

Memory system and method for controlling memory system

An information processing apparatus according to the present invention includes a controller for dividing data into a plurality of divided-data; a plurality of storage units for storing the plurality of divided-data, respectively; a plurality of storage controllers for writing the divided-data into the corresponding storage unit or reading out the divided-data from the respective storage units; a plurality of history storage units for storing histories of the operation of the corresponding storage controllers, respectively; an error detector for detecting an error in the divided-data; an error correction controller for controlling correction of the error; and a plurality of history controller for controlling update of the histories in the corresponding history storage units, respectively upon correction of the error.

Information processing apparatus, history management method

An information processing apparatus includes a data transmitting apparatus that transmits data of an N-bit width; a data receiving apparatus that receives the data of the N-bit width from the data transmitting apparatus; and a data bus of the N-bit width connecting the data transmitting apparatus and the data receiving apparatus. The data transmitting apparatus includes a first error-detection-code-attached data generation circuit, a second error-detection-code-attached data generation circuit, a first degeneration correspondence register, and a transmission-side selection circuit. The data receiving apparatus includes a first error checking circuit, a second error checking circuit, and a second degeneration correspondence register.

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Kawasaki, Japan

Kazuya Takaku