Seiko Epson Corporation

Kazuya Nakamura

Kenji Hayashi

Katsunori Yamazaki

Takashi Aoki

Kiyoshi Nakamura

Hirofumi Hokari

Hiroki Nakahara

Daisuke Abe

Saichi Hirabayashi

An electrophoretic display base includes a base; a partition which is disposed on one surface of the base and in which the opposite side of the one surface is open; an electrophoretic dispersion liquid which contains a dispersion medium and charged particles filled in a cell on the base which is defined by the partition; and a lid which is disposed to block an opening of the partition, and has a porosity capable of passing the electrophoretic dispersion liquid therethrough.

Electrophoretic display base having porous lid

An electrophoretic display includes an electrophoretic layer arranged in each pixel region partitioned by a partition member disposed between a first electrode and a second electrode that are arranged on the inner sides of a pair of substrates. The partition member has bottom portions laminated on the first electrode and partition walls joined to the bottom portions. The partition walls partition the pixel region. The bottom portions each have a protrusion.

Electrophoretic display and electronic device

An active matrix substrate includes a substrate; a plurality of data lines provided on the substrate; a plurality of scanning lines provided to cross the data lines on the substrate when seen in a plan view; a thin film transistor that is electrically connected to one of the plurality of data lines and one of the plurality of scanning lines and has an organic semiconductor layer; a pixel electrode electrically connected to the thin film transistor; and a capacitive element electrically connected in parallel with the thin film transistor between the data line and the pixel electrode.

Active matrix substrate, electrophoretic display apparatus, and electronic device

A thin film transistor includes a source electrode and a drain electrode which are disposed to face each other, an organic semiconductor layer provided at least between the source electrode and the drain electrode, a plurality of gate lines extending over the source electrode, the organic semiconductor layer, and the drain electrode, and a gate insulating layer interposed between the source electrode, the drain electrode, and the organic semiconductor layer and the plurality of gate lines.

Growing community of inventors

Tatsuno-machi, Japan

Kazuya Nakamura