Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kazuya Matsuzawa

Hiroshi Watanabe

Riichiro Shirota

Takao Marukame

Yoshifumi Nishi

Yusuke Higashi

Jiezhi Chen

Atsuhiro Kinoshita

Yuichiro Mitani

Daisuke Hagishima

Naoyuki Shigyo

Yuuichiro Mitani

Takeshi Hamamoto

Yukihito Oowaki

Katsuhiko Hieda

Akira Nishiyama

Yuki Sasaki

Satoshi Inaba

Tohru Ozaki

Kazutaka Ikegami

Atsushi Murakoshi

Masami Aoki

Ken Uchida

Yoshiaki Matsushita

Masamichi Suzuki

Takahiro Kurita

Osamu Arisumi

Toshiyuki Enda

Yutaka Ishibashi

Hirotaka Nishino

Hiroyoshi Tanimoto

Makoto Yoshimi

Shuichi Toriyama

Mamoru Terauchi

Izumi Hirano

Hitomi Kawaguchiya

Takahiro Nakauchi

According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

Memory system, error correction device, and error correction method

An arithmetic control device according to an embodiment controls arithmetic operations using a memory chip. The memory chip includes a memory cell array and a controller. The memory cell array includes a plurality of memory cells. The controller is configured to control access to the memory cell array. The arithmetic control device includes a first writing unit and a first reading unit. The first writing unit requests the controller to write a first value to a second cell near a first cell of the memory cell array. The first reading unit requests the controller to read a second value from the first cell after the first value is written to the second cell.

Arithmetic control device, memory system including the same, information processing device, and arithmetic control method

According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.

Memory system

According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

Semiconductor circuit, D/A converter, mixer circuit, radio communication device, method for adjusting threshold voltage, and method for determining quality of transistor

A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.

Nonvolatile programmable logic switch

An electronic device includes a substrate, a first chip mounted on the substrate and having a first terminal, a second terminal, an input pad and a semiconductor time switch connected to the first terminal and the second terminal and configured to disconnect the first terminal and the second terminal upon lapse of a prescribed lifetime, the input pad being configured to set the prescribed lifetime, a second chip mounted on the substrate and incorporating an operational device having a third terminal connected to the first terminal and a fourth terminal serving as an input terminal for an external device, a first memory device mounted on the substrate, having a fifth terminal connected to the second terminal and storing information required for operating the operational device, and an encapsulater covering at least the input pad of the first chip.

Electronic device which disconnects first and second terminals upon lapse of a prescribed device lifetime

Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided.

Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit

According to an aspect of the invention, a nonvolatile semiconductor memory comprises: a semiconductor substrate; a trench formed in the semiconductor substrate; a first insulating film being formed on a wall surface of the trench; a floating gate electrode formed on the first insulating film inside the trench; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a channel region formed between the source region and the drain region in the semiconductor substrate, a second insulating film formed on a surface of the semiconductor substrate; and a control gate electrode formed on the channel region and a surface of the second insulating film. The channel region is adjacent to the trench. A storage state of the nonvolatile semiconductor memory is formed by injecting or drawing charge into or from the floating gate electrode when a tunnel current flows through the first insulating film.

Nonvolatile semiconductor memory having a floating gate electrode formed within a trench

It is made possible to prevent 'spoofing' and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.

Authenticated device and individual authentication system

It is made possible to provide a non-volatile semiconductor memory device capable of improving the writing efficiency and its writing method. Predetermined voltages are respectively applied to a drain region and a control gate, and then the voltage applied to the control gate is opened.

Non-volatile semiconductor memory device and its writing method

An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is discusssed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or 'shared' by adjacent ones of the serially coupled memory cell transistors.

NAND type nonvolatile semiconductor memory device having sideface electrode shared by memory cells

A data compression apparatus has a characterizing point extracting partwhich extracts data expressing characterizing points included in a plurality of data showing a result of carrying out simulation, quantized data generating partwhich generates quantized data obtained by quantizing data except for data expressing characterizing points, and file number converting partwhich converts the same types of quantized data including in the quantized data, into a relating file number. In the case of compressing data, data except for the characterizing points is compressed. If the same quantized data is included at the same address location in the previously-compressed file, the quantized data is replaced with the file number of previously-compression file, thereby compressing data at high efficiency.

Data retrieving method, data retrieving apparatus, data compression method and data compression apparatus

Semiconductor LSI circuit having a NAND logic gate with a highly integrated and microscopic structure

A semiconductor storage device has a first transistor of first conductive type which control data writing, a second transistor of second conductive type which controls data read-out, a third transistor which amplifies a current corresponding to data to be read out, a first semiconductor layer which is disposed in a predetermined direction, in which a gate of the first transistor is formed, a second semiconductor layer which is disposed separately from the first semiconductor layer in the predetermined direction, in which source and drain of the second transistor and source and drain of the third transistor are formed, a write transistor forming region which is disposed in a direction intersecting the first and second semiconductor layers, in which source and drain of the first transistor, a gate of the third transistor and an electric charge storing region storing electric charge in accordance with data to be written are formed, and a read-out transistor gate region which is disposed in a direction intersecting the first and second semiconductor layers, in which a gate of the second transistor is formed.

Semiconductor storage device

A data compression apparatus includes a characterizing point extracting part which extracts data expressing characterizing points included in a plurality of data showing a result of carrying out simulation a quantized data generating part which generates quantized data obtained by quantizing data except for data expressing characterizing points, and a file number converting part which converts the same types of quantized data including in the quantized data, into a relating file number. During data compression, data except for the characterizing points is compressed. If the same quantized data is included at the same address location in the previously-compressed file, the quantized data is replaced with the file number of the previous compression file, thereby compressing data at high efficiency.

Growing community of inventors

Kawasaki, Japan

Kazuya Matsuzawa