Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Kazuya Kodani

Hitoshi Matsumura

Atsushi Yamamoto

Hiroshi Matsuyama

Eitaro Miyake

Tatsuya Hirakawa

Yuuji Hisazato

Yo Sasaki

Ichiro Omura

Masayuki Tobita

Tomokazu Domon

Nobumitsu Tada

Daisuke Hiratsuka

Makoto Takeda

Nobuhiro Shingai

Toshiaki Matsumoto

Hiroaki Ito

Toshiharu Ohbu

Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth connecting portion provided between the second plate portion and the fourth plate portion and connecting the second plate portion and the fourth plate portion; and a fifth plate portion provided above the fourth plate portion, the fifth plate portion connected to the fourth plate portion, and the fifth plate portion having a hole.

Terminal plate and semiconductor device

A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor elements provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal.

Semiconductor device

A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.

According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.

Semiconductor device and method for manufacturing the same

According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.

Semiconductor device and manufacturing method of semiconductor device

According to one embodiment, a heatsink includes a base and heat radiation fins placed on one of surfaces of the base and arranged in parallel to each other with a submillimeter narrow pitch. Each of the multiple heat radiation fins has a submillimeter thickness, a length in a width direction of 60 mm or smaller, and a height of 40 mm or smaller. The heatsink assembly may be constituted by allaying a plurality of the heatsinks and thermally connecting each of the heatsinks to each other using a heat transport device.

Heatsink, heatsink assembly, semiconductor module, and semiconductor device with cooling device

A current detection equipment comprises a first coil and a second coil connected in series with the first coil. The current detection equipment is capable of detecting a current flowing through an object which is provided between the first and second coils or provided in a vicinity of the first or second coil. Each of the first and second coils having first conductive patterns provided on a surface of a substrate, a second conductive patterns provided on a back of the substrate and connecting parts which connect the first and second conductive patterns. A semiconductor device including the current detection equipment to measure the current flowing in a semiconductor element is also proposed.

Current detection equipment and semiconductor device

A power semiconductor module comprises a wide band gap semiconductor chip having its surface with an electrode provided thereon, and more than one bonding wire which is connected to an edge portion of the electrode directly or indirectly via an electrode pad. The electrode and the electrode pad have their thickness values that are specifically set in such a way as to obtain a conduction area ratio equal to or greater than a conduction area ratio of the wide band gap semiconductor chip in the case where a respective one of the electrode and electrode pad is made of aluminum while letting a total thickness value of the electrode and the electrode pad measure ten micrometers (10 &#x3bc;m).

Power semiconductor module

A double circular gate conductor 9 comprises a first circular gate conductor 7 connected to a gate electrode 2a, a second circular gate conductor 8, and a connecting conductor which connects the first circular gate conductor 7 and the second circular gate conductor 8, and is configured so as to equalize the voltage drop due to self-inductance or mutual inductance between the first circular gate conductor 7, second circular gate conductor 8 and cathode post electrode 4. In this manner it is possible to guarantee more or less uniform parallel inductance over the surface of the element.

Growing community of inventors

Kawasaki, Japan

Kazuya Kodani