Sharp Kabushiki Kaisha Corporation

National Institute of Advanced Industrial Science and Technology

Elpida Memory, Inc.

Xenogenic Development Limited Liability Company

Kanazawa University

Kazuya Ishihara

Nobuyoshi Awaya

Shinobu Yamazaki

Mitsuru Nakura

Takashi Nakano

Yasunari Hosoi

Suguru Kawabata

Yoshiji Ohta

Shigeo Onishi

Yukio Tamai

Tetsuya Ohnishi

Takahiro Takimoto

Kazuhiro Natsuaki

Masayo Uchida

Takahiro Shibuya

Junya Onishi

Keizo Sakiyama

Masaya Nagata

Shinji Kobayashi

Jun Kudo

Hiroyuki Akinaga

Shigeo Ohnishi

Yushi Inoue

Akiyoshi Seko

Hisashi Shima

Yutaka Ishikawa

Fumiyoshi Takano

Tetsu Miyoshi

Masaya Komai

Takeshi Kijima

Kenichi Tanaka

Kenji Mae

Akira Okutoh

Nobuhito Ogata

Yoshiaki Tabuchi

Tsutomu Yamadai

Akio Kitagawa

Kazuya Nakayama

Takahiro Shibiuya

A photoelectric conversion device includes: a first optical filter that has a first pattern periodically having a plurality of structures and is formed of a conductive material film disposed on a first photoelectric conversion element with an insulating film therebetween; and a first optical filter that has a second pattern periodically having a plurality of structures and is formed of a conductive material film disposed on a second photoelectric conversion element with the insulating film therebetween. The interval between the first pattern and the second pattern that are adjacent to each other is longer than a period of the structures in the first pattern and a period of the structures in the second pattern.

Photoelectric conversion device

A photoelectric conversion device capable of preventing anomalous transmission of light of a wavelength that is not supposed to be transmitted and reducing the half-width of a spectral waveform and a method for manufacturing such a photoelectric conversion device are provided. A first photoelectric conversion element is formed on a substrate. A first metal film having a plurality of openings arranged periodically or aperiodically is formed above the first photoelectric conversion element with insulating films interposed therebetween. A second metal film covering a part of the openings in the first metal film is provided.

Photoelectric conversion device and method for manufacturing same

An optical filter configured to transmit light of a predetermined wavelength includes a substrate; a first conductive thin film that is disposed on the substrate and has apertures extending through the first conductive thin film and arranged with a period of less than the predetermined wavelength; and a second conductive thin film at least a portion of which faces the apertures so as to be separated from the apertures.

Optical filter configured to transmit light of a predetermined wavelength

A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof.

Semiconductor device and control method for semiconductor device

A semiconductor memory device includes a writing circuit and a reading circuit. The writing circuit executes a setting action for converting a resistance of a variable resistance element to a low resistance by applying current from one end side to the other end side of a memory cell via the variable resistance element, and a resetting action for converting the resistance to a high resistance by applying current from the other end side to the one end side via the variable resistance element. The reading circuit executes a first reading action for reading a resistance state of the variable resistance element by applying current from one end side to the other end side of the memory cell via the variable resistance element, and a second reading action for reading the resistance state by applying current from the other end side to the one end side via the variable resistance element.

Semiconductor memory device and semiconductor device

A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

Variable resistive element, and its manufacturing method

A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix, each memory cell being configured such that a variable resistance element and a selection transistor are connected in series. A set operation for a memory cell (an operation of converting the resistance of the variable resistance element to a low resistance) is performed by applying a set voltage pulse for a longer time than that for a reset operation (an operation of converting the resistance of the variable resistance element to a high resistance) while limiting, using the selection transistor, an electric current flowing in the set operation to a certain low electric current, and by simultaneously applying the set voltage pulse to the plurality of memory cells.

Semiconductor memory device

A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.

Method of forming process for variable resistive element and non-volatile semiconductor memory device

The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.

Nonvolatile semiconductor memory device

In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.

The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.

Non-volatile semiconductor device

Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.

A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.

Growing community of inventors

Osaka, Japan

Kazuya Ishihara