Rohm Co., Ltd.

Kazuya Ioki

Hiromitsu Kimura

Kazutoshi Kobayashi

Jun Furuta

Ryuichi Nakajima

A flip-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.

Flip-flop circuit, semiconductor integrated circuit device, and vehicle

Disclosed is a data storage circuit that stores target input data inputted to a data input terminal and outputs the stored data as target output data through a data output terminal. The data storage circuit includes a clock control circuit that outputs a master clock signal and a slave clock signal based on a reference clock signal, a master latch circuit that takes the target input data based on the master clock signal, holds the taken data, and outputs the taken data as master output data, a slave latch circuit that takes the master output data based on the slave clock signal, holds the taken data, and outputs the taken data as slave output data, and an output data generation circuit that generates the target output data.

Data storage circuit and electronic apparatus

Disclosed is a flip flop circuit including a master latch circuit receiving master input data based on target input data, a slave latch circuit configured to load master output data from the master latch circuit and to hold the master output data, and a data output section, target output data based on the target input data being output from the data output section. The slave latch circuit includes a first to an N-th slave latch circuits provided in parallel with the master latch circuit (N is an integer of 2 or larger), the flip flop circuit further includes an output selection circuit selecting any one of data output from the first to N-th slave latch circuits, and selection data from the output selection circuit is output from the data output section as the target output data.

Growing community of inventors

Kyoto, Japan

Kazuya Ioki