Mitsubishi Electric Corporation

Kazuya Hokazono

Dong Wang

Akihisa Yamamoto

Jun Fukudome

Mitsutaka Hano

Yuki Terado

A semiconductor device drive circuit includes: a first transistor and a second transistor operating complementarily between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit operating between the first voltage and the second voltage, and including: a constant voltage generation unit outputting an internal power supply voltage steadily being a constant voltage; and a feedback unit receiving a node voltage of a connection node between the first transistor and the second transistor, and changing the internal power supply voltage output from the constant voltage generation unit in response to a change of the node voltage; and a pre-driver operating between the first voltage and the internal power supply voltage, and driving the first transistor or the second transistor, wherein the node voltage is output as a gate voltage of the power switching device.

Semiconductor device drive circuit

A semiconductor device includes a first switch and a first driver. The first switch selects and outputs one of a power supply potential and a generated potential as a first switch output potential based on a synchronization signal from a transmission circuit and a delayed signal delayed from the synchronization signal. The first driver charges a gate of a bipolar transistor element based on the synchronization signal of the transmission circuit and the first switch output potential.

Semiconductor element driving circuit and semiconductor element driving device

An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.

An object of the present invention is to reduce a chip area of the high-side driver circuit. A high-side driver circuit of the present invention is a high-side driver circuit in which a first potential is set as a power supply potential, which includes a constant voltage circuit configured to operate with a second potential as a reference potential, and generate, from the first potential, a third potential which is lower than the first potential and higher than the second potential, a logic circuit configured to operate with the third potential as a reference potential, a level shift circuit configured to shift the reference potential of the output signal of the logic circuit from the third potential to the second potential, and a driver circuit in which the second potential is set as a reference potential, and configured to drive a switching element by the output signal.

High-side driver circuit

A semiconductor device driving circuit includes: a signal transmission circuit including a first level shift circuit, the signal transmission circuit and an unsaturated voltage detection circuit configured to output a first error signal when an unsaturated voltage of a semiconductor switching element driven by the drive signal is detected. The semiconductor device driving circuit generates a second error signal having the second voltage level by level-shifting the first error signal or a converted signal obtained by converting the first error signal into a pulse signal. The semiconductor device driving circuit further includes a soft shutdown circuit configured to change a drive signal for the semiconductor switching element to softly shut down the semiconductor switching element when the second error signal is input.

Semiconductor device driving circuit

A semiconductor device drive circuit drives a semiconductor switching device including a first electrode, a second electrode, and a control electrode. The semiconductor device drive circuit includes an input terminal that receives an input signal; a level shift unit that shifts a voltage level of the input signal and outputs a drive signal to be supplied to the control electrode; a first resistor that generates a first current from a first voltage applied to the first electrode; a second resistor that generates a second current from a second voltage applied to the second electrode; and a voltage difference determination unit that outputs a detection signal when a difference between the first current and the second current is equal to or greater than a predetermined desaturation determination value. The semiconductor device drive circuit is a single integrated circuit chip.

Semiconductor device drive circuit and inverter device with desaturation detection

A delay-time correction circuit delays an input signal for generating a pre-drive signal to a drive unit generating a drive signal. A transition-change sensor senses a transition change in one of a turn-on operation and turn-off operation. A correction-signal generator generates a correction signal in response to the transition change sensed by the transition-change sensor and to the input signal. A delay output unit generates an output signal corresponding to the pre-drive signal by delaying the input signal using the correction signal. The delay output unit delays the output signal that instructs the other of a turn-on operation and turn-off operation, from the input signal, in accordance with a length of a period for the transition change in the one of a turn-on operation and turn-off operation that is performed immediately before the other of a turn-on operation and turn-off operation.

Delay-time correction circuit, semiconductor-device drive circuit, and semiconductor device

A semiconductor device driving circuit includes: a threshold adjustment circuit; a desaturation voltage detection circuit; and a drive circuit. The threshold adjustment circuit switches the threshold between a first voltage and a second voltage which is larger than the first voltage, outputs the first voltage as the threshold when the semiconductor switching device is in an off-state, and outputs the second voltage as the threshold when the semiconductor switching device is turned on and a voltage between the first electrode and the second electrode is a saturation voltage.

A level shift circuit includes: an electrothermal converter converting a first electric signal with a first reference potential as a reference to heat; a thermoelectric converter converting the heat from the electrothermal converter to a second electric signal with a second reference potential which is different from the first reference potential as a reference; and an insulating region electrically insulating the electrothermal converter from the thermoelectric converter.

Level shift circuit and drive circuit

A semiconductor device drive circuit includes a first drive circuit and a second drive circuit. The first drive circuit generates a control signal for controlling a voltage-controlled switching element. The first drive circuit generates a control signal in synchronization with a voltage signal input to the first drive signal. The first drive circuit has an output current capability corresponding to a magnitude of the voltage signal. The second drive circuit outputs a voltage signal to the first drive circuit. The second drive circuit includes an output adjustment circuit that adjusts the magnitude of the voltage signal.

A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.

Level shift circuit, integrated circuit, and power semiconductor module

A semiconductor device employs at least one of semiconductor chip groups. The semiconductor device includes a semiconductor chip included in the semiconductor chip groups, and a package. The semiconductor chip includes an information recording region on which is recorded a first piece of identification information indicating to which group of the semiconductor chip groups the semiconductor chip belongs based on a first category. The information recording region includes a plurality of fuses selectively blown in accordance with the first piece of identification information. Indicated on the package is a second piece of identification information indicating to which group of the semiconductor chip groups the semiconductor chip belongs based on a second category. The first and second pieces of identification information are combined together to identify the semiconductor chip from among the semiconductor chip groups.

Semiconductor device, and semiconductor chip having chip identification information

A primary circuit produces a first on-pulse and a first off-pulse synchronized with a rising edge and a falling edge of an input signal, respectively. A level shift circuit produces a second on-pulse and a second off-pulse formed by shifting the voltage level of the first on-pulse the first off-pulse, respectively. A secondary circuit outputs an output pulse rising and falling in synchronization with the second on-pulse and the second off-pulse, and holds the output when both of the pulses are high. When the reference potential rises, the pulse corresponding to the state of the input signal during the rise of the second potential in the first on-pulse and the first off-pulse is regenerated and one of the second on-pulse and the second off-pulse is thereby made high after the end of the rise of the second reference potential to retransmit the state of the input signal.

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Tokyo, Japan

Kazuya Hokazono