Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kazuya Hatooka

Kenji Murata

Shoichi Yoshizaki

Michiyo Yamamoto

Koki Imamura

A clock and data recovery circuit includes a multiphase clock generator circuit which generates a multiphase clock having a plurality of clocks, a sampling circuit which samples a received data signal transferring serial data in synchronism with each of the plurality of clocks, and generates a plurality of data signals, a data recovery unit which generates a selection signal indicating a data signal having an appropriate phase among the plurality of data signals, and a storage unit which stores the selection signal. The data recovery unit selects one of the plurality of data signals, based on the selection signal read from the storage unit, and a clock corresponding to the selected data signal.

Clock and data recovery circuit

The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating the detection result; a threshold adjustment control section for generating the first detection level adjustment signal in response to the detection signal and outputting the generated signal; and a detection section for detecting whether or not the level of the detection signal changes repeatedly. During the time of no input of the differential signal, the threshold adjustment control section changes the first detection level adjustment signal so that the threshold voltage monotonically increases or decreases until the detection signal is inverted, to determine the first detection level adjustment signal that makes the threshold voltage appropriate, and outputs the determined signal.

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Hyogo, Japan

Kazuya Hatooka