Kabushiki Kaisha Tokai Rika Denki Seisakusho

Kazuya Adachi

Kengo Shima

Narumasa Soejima

Yoshikazu Kataoka

Takashi Suzuki

Yosuke Kanie

Yuto Hakamata

An electrostatic protection element including: a first impurity layer of second conductivity type formed on a semiconductor substrate of first conductivity type; a second impurity layer of the first conductivity type formed within the first impurity layer; a first contact layer of the first conductivity type formed in a region within the first impurity layer other than at the second impurity layer; a second and a third contact layer both of the second conductivity type and formed within the second impurity layer; and multilayer wiring connected through a stack structure to the first, the second, and the third contact layer, wherein the stack structure includes at least a first layer wiring connected to each of the first, the second, and the third contact layer, and a second layer wiring connected to the first layer wiring directly above each of the first, the second, and the third contact layer.

Electrostatic protection element

A semiconductor integrated circuit including: a substrate of a first conductivity type; a buried insulating film provided on the substrate; an active layer of the first conductivity type provided on the buried insulating film; a first impurity region of a second conductivity type formed within the active layer; an electric field relaxation layer of the second conductivity type formed within the active layer and surrounding the first impurity region; a second impurity region of the first conductivity type formed within the active layer and surrounding the electric field relaxation layer; and a groove formed surrounding the second impurity region and reaching the buried insulating film.

Semiconductor integrated circuit

A protection device includes a semiconductor substrate including a protection element; an insulating layer covering a surface of the semiconductor substrate; a conductive layer disposed in the insulating layer, and extending in a plane that is parallel with the surface of the semiconductor substrate; a passive element formed with an elongated conductor, curved in a plane that is parallel with the conductive layer, and located over the conductive layer; and an input terminal, an output terminal, and a ground terminal exposed in a surface of the insulating layer. One end of the passive element is electrically connected to the input terminal, the other end of the passive element and a high-potential-side terminal of the protection element are electrically connected to the output terminal, and a low-potential-side terminal of the protection element and the conductive layer are electrically connected to the ground terminal.

Growing community of inventors

Aichi, Japan

Kazuya Adachi