Sony Corporation

Kazutoshi Shimizume

Mamoru Akita

Shinobu Nakamura

Takaaki Yamada

Masahiko Itoh

Kazuyuki Miyazawa

Yoichiro Sako

Takashi Okada

Junichi Aramaki

Shozo Masuda

Osamu Akimoto

Akira Ishizuka

Kazuhiro Yasuda

Naoki Ando

Hideaki Kawaura

Hidenobu Noda

Hirokazu Kuroda

Ikuro Hata

Mutsumi Kimura

Yoshinori Tsuboi

Shinichi Koga

Shigeru Inohana

Katsuhisa Hirano

Takeshi Uematsu

Tetsu Haga

Noriaki Horiguchi

Youhei Hasegawa

Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals INto INare supplied to diffusion layer regionsandvia transistorsto, and are accumulated as electric charge. A clock signal is applied to signal linesandalternately connected to gate electrodesto, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifierstoare connected to the diffusion layer regionsand, and the accumulated electric charge is converted into voltage and is output to output terminals VOUTto VOUTas analog signals. A scan-in terminal Sin is connected to a diffusion layer region, and a scan-out terminal Sout is connected to the diffusion layer regionvia an electric charge/voltage conversion amplifier

Analog scan circuit, analog flip-flop, and data processing apparatus

A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Semiconductor memory system and signal processing system

Disclosed herein is a liquid crystal display apparatus, including, a pixel array section, a first data line, a second data line, a writing unit, a voltage supply control unit, a data line short-circuiting unit, a reading out unit, and a testing unit.

Liquid crystal display apparatus and testing method for liquid crystal display apparatus

The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Semiconductor device, semiconductor integrated circuit and bump resistance measurement method

A defective pixel examination method includes the steps of applying different voltages to a capacitive element of a first pixel section and a capacitive element of a second pixel section among the plurality of pixel sections; turning on a switch provided between an input electrode of a pixel transistor in the first pixel section and an input electrode of a pixel transistor in the second pixel section and short-circuiting the input electrode of the first pixel transistor and the input electrode of the second pixel transistor; reading a voltage of the capacitive element of the first pixel section and a voltage of the capacitive element of the second pixel section; and detecting defects of a pixel section on the basis of the result of the comparison between the voltage of the capacitive element of the first pixel section and the voltage of the capacitive element of the second pixel section.

Liquid-crystal display device, defective pixel examination method, defective pixel examination program, and storage medium

The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and transferring the main code words to one of a plurality of memory banks. The semiconductor device also includes a data output portion for receiving one page worth of data, including main code words transferred from the data latch circuit, correcting errors in the data when the data includes fewer than a predetermined number of errors for each main code word, adding the error information to each read code word, and outputting the result.

Semiconductor memory device and signal processing system

A semiconductor device includes on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, where a plurality of logic circuits having the same functions or different functions are mounted in the active regions on the same chip.

Semiconductor device carrying a plurality of circuits

MOS transistors A and B form a transistor circuit (an inverter in this case). A MOS transistor D is one for interrupting leakage current that has a channel length longer than those of the MOS transistors A and B. Under the action of an enable terminal (Enable), the MOS transistor D conducts only while the circuit is operated, and does not conduct and thereby interrupts leakage current while the circuit is in a standby state. A MOS transistor C does not produce effect while the circuit is operated, and makes the potential of an output terminal (Output) a high potential or a low potential (not intermediate potential) only while the circuit is in the standby state. Therefore, the circuit controls unnecessary through-transistor current of a standby type circuit in a succeeding stage, which current is conventionally caused at an intermediate potential during standby.

Transistor circuit

A servo control system for a shock-proof disk player comprising a digital signal processor, a voltage-controlled oscillator, a reference clock generator, a clock mode changeover switch, a phase comparator for controlling a head-rotating spindle motor, and a bulk memory of a large capacity for storage of data, wherein the phase lock of a PLL at the time of a seek is switched on or off under control to thereby shorten the required seek time. The clock signal frequency is selectively changed in such a manner as to lock the PLL in accordance with the rotation rate, whereby the power consumption can be lowered. The bulk memory is used as a data buffer, and the servo system is controlled as the data are read out from the memory while the data quantity stored and left therein is detected, so that a reduction of the power consumption can be achieved with another advantage of enhancing the resistance against shock.

Servo control system for disk player

An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter etc. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.

Phase modulator circuit

An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.

A disc reproducing apparatus such as a disc player and a method of the same which of the seek time can be shortened at the time of traverse of a pick-up, by calculating a line speed at a read position of a disc before the change of the read position and the target line speed after the change of the read position before the pick-up is traversed, controlling the rotational speed of a rotation driving unit to that before the change of the read position so that the line speed at the read position after the change falls within a maximum reproduction line speed.

Disc reproducing apparatus and method with adjustment of rotation speed

In a disk recording/reproduction apparatus, the operational limit of each of a mechanical apparatus and signal processing of a disk drive is taken into consideration. When an area from the innermost region of a disk to a predetermined distance is recorded or reproduced, the disk is rotationally driven by a CAV method, and when an area from the predetermined distance of the disk to the outermost region is recorded or reproduced, the disk is rotationally driven by a CLV method.

Disk driving system and disk driving method

A disc reproduction apparatus, configured so that a voltage-controlled oscillator is used as a means of giving a reference frequency to an analog phase-locked loop circuit, a control voltage based on a speed error of the rotational speed of a spindle with respect to the reference speed is given to this voltage-controlled oscillator by a rotational speed counting circuit, and a reference clock is produced in the analog phase-locked loop circuit based on the oscillation frequency given by this voltage-controlled oscillator and, at the same time, the reproduction clock PLLCK is produced by the digital phase-locked loop circuit based on this reference clock, whereby the operation becomes stable with respect to rotational outer disturbances and high speed access is enabled.

Disc player apparatus having a disc rotational speed controller

A disc reproduction apparatus, configured so that a voltage-controlled oscillator is used as a device of giving a reference frequency to an analog phase-locked loop circuit, a control voltage based on a speed error of the rotational speed of a spindle with respect to the reference speed is given to this voltage-controlled oscillator by a rotational speed counting circuit, and a reference clock is produced in the analog phase-locked loop circuit based on the oscillation frequency given by this voltage-controlled oscillator and, at the same time, the reproduction clock PLLCK is produced by the digital phase-locked loop circuit based on this reference clock, whereby the operation becomes stable with respect to rotational outer disturbances and high speed access is enabled.

Growing community of inventors

Kanagawa, Japan

Kazutoshi Shimizume