Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Kazutoshi Oomori

Hideo Aoki

Tsuyoshi Tamaru

Takayuki Oshima

Noriko Miura

Tsuyoshi Fujiwara

Yoshinori Hoshino

Katsuyuki Asaka

Yasuhiro Nariyoshi

A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

Method of manufacturing a semiconductor device

It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750&#xb0; C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60&#xb0; C./second or less.

Method for manufacturing semiconductor integrated circuit device

A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

Semiconductor integrated circuit device

It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750&deg; C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

Growing community of inventors

Ome, Japan

Kazutoshi Oomori