Fujitsu Semiconductor Limited

Fujitsu Corporation

Fujitsu Microelectronics Limited

Kazutoshi Izumi

Naoya Sashida

Aki Dote

Hitoshi Saito

Kouichi Nagai

Tetsuya Takeuchi

Kaoru Saigoh

Yukinobu Hikosaka

Masahiko Doki

Mitsushi Fujiki

Katsuyuki Karakawa

Kouichi Koseko

Yasuhiro Hayashi

Koichiro Ohira

An insulation film () having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor () is formed. Thereafter, an alumina film () is formed on the insulation film (). According to the method, low coverage of the alumina film () does not become a problem, and the ferroelectric capacitor () is reliably protected.

Semiconductor device and manufacturing method thereof

A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.

Semiconductor device and method of manufacturing the same

Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of: forming a hydrogen diffusion preventing insulating film covering capacitors; forming a capacitor protecting insulating film on the hydrogen diffusion preventing insulating film; and forming a first insulating film on the capacitor protecting insulating film by a plasma CVD method where, while a high-frequency bias electric power is applied toward the semiconductor substrate, a plasma-generating high frequency electric power is applied to first deposition gas containing oxygen and silicon compound gas. In the method, a condition by which moisture content in the capacitor protecting insulating film becomes less than that in the first insulating film is adopted as a film deposition condition for the capacitor protecting insulating film.

After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.

Manufacturing method of semiconductor device

The embodiments discussed herein reduce, in a semiconductor device having a ferroelectric capacitor, the film thickness of an interlayer insulation film covering the ferroelectric capacitor without degrading yield, and reduce the invasion of water into the ferroelectric capacitor. A semiconductor device includes a first interlayer insulation film formed on a substrate, a ferroelectric capacitor formed on the first interlayer insulation film, a second interlayer insulation film formed on the first interlayer insulation film so as to cover the ferroelectric capacitor, and a hydrogen barrier film formed on the second interlayer insulation film, the ferroelectric capacitor is formed of a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film in contact therewith, and a polish-resistant film formed on the upper electrode, wherein the second interlayer insulation film covers the polish-resistant film with a film thickness of 50-100 nm.

Semiconductor device and semiconductor product

A method of measuring a film thickness is disclosed. The method includes a step of forming a ferroelectric capacitor on a substrate, a step of forming an insulating film to cover the ferroelectric capacitor, and a step of optically measuring the thickness of the insulating film on an electrode of the ferroelectric capacitor.

Method of measuring film thickness and method of manufacturing semiconductor device

After forming an interlayer insulating film () covering a ferroelectric capacitor, a hydrogen diffusion preventing film (), an etching stopper () and an interlayer insulating film () are formed. Then, a wiring having a tantalum nitride (TaN) film () (barrier metal film) and a copper (Cu) film () is formed in the interlayer insulating film () by a single damascene method. Thereafter, a wiring having a copper film () and a wiring having a copper film () and the like are formed by a dual damascene method.

Semiconductor device for non-volatile memory and method of manufacturing the same

An interlayer insulating film made of insulating material is formed on a semiconductor substrate. A hydrogen diffusion barrier film is formed on the interlayer insulating film, the hydrogen diffusion barrier film being made of material having a higher hydrogen diffusion barrier function than a hydrogen diffusion barrier function of material of the interlayer insulating film. The semiconductor substrate formed with the interlayer insulating film and hydrogen diffusion barrier film is thermally treated. In the process of forming the interlayer insulating film, the interlayer insulating film is formed under the condition that a moisture content becomes 5&#xd7;10g/cmor lower. Even if annealing is performed after the hydrogen diffusion barrier film is formed, a crack is hard to be formed in the underlying interlayer insulating film.

Semiconductor device having interlayer insulating film covered with hydrogen diffusion barrier film and its manufacture method

A stacked film of a first insulation film being a silicon oxide film with an extremely low moisture content, and a second insulation film being a silicon oxide film with a higher moisture content than the first insulation film, therefore, with a low in-plane film thickness distribution rate is formed, and this is polished by CMP. Polishing is performed until the second insulation film is wholly removed directly above a ferroelectric capacitor structure and a surface of the first insulation film is exposed to some extent. At this time, surface flattening is performed for a top surface of a first portion in the first insulation film and a top surface of the second insulation film, and an interlayer insulation film constituted of the first insulation film and the second insulation film remaining on a second portion of the first insulation film is formed.

Semiconductor device and manufacturing method of the same

A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.

Semiconductor device having ferroelectric capacitor and its manufacture method

A highly reliable semiconductor device having a ferroelectric capacitor structure by sufficiently preventing the Hattack without damaging the function of an interlayer insulating film covering interconnections and the like to obtain a high capacitor performance. The position of a semiconductor substrate mounted on and secured to a substrate support plate in an HDP-CVD system is adjusted in the vertical direction, whereby a second HDP-CVD oxide film is deposited so that voids are formed between aluminum interconnections at lower positions than the height of the aluminum interconnections.

Method of fabricating an interconnection layer above a ferroelectric capacitor

A method of manufacturing a semiconductor device has the steps of: forming a wiring pattern by dry etching a wiring layer on a semiconductor substrate, using a resist pattern as a mask; immersing the wiring pattern in amine containing liquid to remove deposition residues formed during the dry etching; then, processing the wiring pattern with fluid not containing amine and being capable of removing deposition residues; forming a conformal insulating layer on the processed wiring pattern; and forming an insulating layer having a planarizing function on the conformal insulating layer by CVD. This method is suitable for multi-layer wiring, and can form an interlayer insulating film having a satisfactory planarizing function.

Growing community of inventors

Kawasaki, Japan

Kazutoshi Izumi