Hitachi, Ltd.

Renesas Electronics Corporation

Renesas Technology Corp.

Kazutoshi Itou

Ryoichi Kajiwara

Hiroshi Hozoji

Shigehisa Motowaki

Hiroi Oka

Asao Nishimura

Kazuya Takahashi

Toshiaki Ishii

Toshiaki Morita

Kazuhiro Suzuki

Masahiro Koizumi

Yuichi Yato

Takuya Nakajo

Hidemasa Kagii

Hiroyuki Nakamura

Ryouichi Kajiwara

Akihiko Narisawa

Masayoshi Shinoda

A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 &#x3bc;m to 200 &#x3bc;m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260&#xb0; C. and reliability under thermal cycle test can be ensured without using lead.

Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material

A fabrication method for a resin encapsulated semiconductor device includes the steps of: (1) die-bonding a semiconductor device to a first electrical connection metallic terminal of a wiring substrate; (2) electrically connecting an electrode of the semiconductor device and a second electrical connection metallic terminal of the wiring substrate via an electrical connector; (3) surface treating such an assembly by applying a solution to a surface of the assembly and baking the applied solution; and (4) transfer-molding an insulating encapsulating resin onto the surface-treated assembly.

Fabrication method for resin-encapsulated semiconductor device

A fabrication method for a metal-base/polymer-resin bonded structured body according to the present invention includes the steps of: (1) applying, to a surface of the metal base, a solution containing an organometallic compound decomposable at 350&#xb0; C. or lower; (2) baking the applied solution in an oxidizing atmosphere to form, on the surface of the metal base, a coating containing an oxide of the metal of the organometallic compound; (3) providing the polymer resin on the coating; and (4) hardening the polymer resin to provide the metal-base/polymer-resin bonded structured body.

Metal-resin-boned structured body and resin-encapsulated semiconductor device, and fabrication method for them

The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280&#xb0; C. or more, and the bondability at 400&#xb0; C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %&#x2266;Sb/(Sn+Sb)&#x2266;48 wt %, 5 wt %&#x2266;Ag&#x3c;20 wt %, 3 wt %&#x2266;Cu&#x3c;10 wt %, and Ag+Cu&#x2266;25 wt %.

High-temperature solder, high-temperature solder paste and power semiconductor using same

A power semiconductor module and an inverter apparatus in which a device or a joining part is not mechanically damaged even when the temperature in use becomes a high temperature in the range of 175 to 250&#xb0; C., resulting in excellent reliability at high temperature retaining test and thermal cycling test. Low thermal expansion ceramic substrates are disposed above and below the device. A material having a coefficient of thermal expansion of 10 ppm/K or less is disposed between the ceramic substrates. In addition, an inorganic material having a coefficient of thermal expansion in the range of 2 to 6 ppm/K or less is disposed around the device.

Power semiconductor module

Pb free solder is used in die bonding. A thermal stress reduction plate is disposed between a semiconductor chip and a die pad made of a Cu alloy. The semiconductor chip and the thermal stress reduction plate are joined and the thermal stress reduction plate and the die pad are joined by a joint material of Pb free solder having Sn&#x2014;Sb&#x2014;Ag&#x2014;Cu as its main constituent elements and having a solidus temperature not lower than 270&#xb0; C. and a liquidus temperature not higher than 400&#xb0; C. Thus, die bonding can be performed using the Pb free solder without generating any chip crack.

Semiconductor apparatus and manufacturing method

In a semiconductor device in which an LSI chip comprising electrodes with a 100 &mgr;m pitch or less and 50 or more pins is mounted directly on an organic substrate, a mounting structure and a manufacturing method thereof are provided excellent in the solder resistant reflow property, temperature cycle reliability and high temperature/high humidity reliability of the semiconductor device. Electrode Au bumps of the chip and an Au film at the uppermost surface of connection terminals of the substrate are directly flip-chip bonded by Au/Au metal bonding and the elongation of the bonded portion of the Au bump is 2 &mgr;m or more. The method of obtaining the bonded structure involves a process of supersonically bonding both of the bonding surfaces within 10 min after sputter cleaning, under the bonding conditions selected from room temperature on the side of the substrate, room temperature to 150&deg; C. on the side of the chip, a bonding load of &frac12;S&times;100 MPa to S&times;180 MPa (S: contact area between bump and chip), a loading mode increasing during bonding, and supersonic application time of 50 to 500 ms.

Semiconductor device and manufacturing method thereof

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Hitachi, Japan

Kazutoshi Itou