Seiko Instruments Inc

Kazutoshi Ishii

Yasuhiro Moya

Jun Osanai

Yoshikazu Kojima

Yuichiro Kitajima

Yukimasa Minami

Miwa Wake

Keisuke Uemura

Yoshihide Kanakubo

Toshihiko Omi

Tatsuya Kitta

Sumitaka Gotou

Masaaki Kamiya

Naoto Inoue

Shoji Nakanishi

Kiyoaki Kadoi

Kentaro Kuhara

Takao Akiba

Koushi Maemura

Yutaka Saito

Yutaka Saitoh

Hisashi Hasegawa

Hitomi Watanabe

Naoto Saitoh

Sumio Koiwa

Sumitaka Goto

Tetsuo Shioura

Tatuya Kitta

In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer through BPSG densification during formation of the interlayer insulating film. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

Method for manufacturing semiconductor device

In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.

A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.

Manufacturing method for a semiconductor device

An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order. According to the present invention, provided are a semiconductor device, including: a semiconductor substrate; an epitaxial layer having an electric polarity identical with that of the semiconductor substrate, which is formed on the semiconductor substrate; a buried diffusion layer having the electric polarity different from that of the semiconductor substrate, which is formed between the semiconductor substrate and the epitaxial layer; and a well region having the electric polarity identical with that of the buried diffusion layer, which is formed above the buried diffusion layer and is electrically connected therewith, in which a MOS transistor is formed in a well having a structure in which the buried diffusion layer is electrically connected with the well region, and a manufacturing method therefor.

Semiconductor integrated circuit device having MOS transistor

Method for manufacturing semiconductor device utilizing monitor wafers

Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.

Semiconductor device and method of manufacturing the same

In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal. Thus, the power management semiconductor device or analog semiconductor device, which is advantageous in terms of cost, manufacturing period and element performance in comparison with the conventional CMOS with an N&plus;polycrystalline silicon gate single polarity or the same polarity gate CMOS in which a channel and a gate electrode have the same polarity, can be realized.

Complementary MOS semiconductor device

A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Semiconductor device and method of fabricating the same

A semiconductor device is provided in which each of contacts between a source and a drain of a MOS transistor and a metallic wiring is either a contact having an arbitrary one side longer than the other side, or source contacts and well contacts are made batting contacts each having an arbitrary one side of a diffusion region having the same polarity as that of a well shorter than the other side. Thus, the contact shape is longitudinal in a transistor width direction, which makes it possible that a large current is caused to flow with a small interval of gates thereof.

Semiconductor device

Method of manufacturing semiconductor device employing oxygen implantation

There is provided a semiconductor integrated circuit device with high electrostatic resistance. A semiconductor device is provided with a transistor for input-output protection having a desired size in which its channel length is varied with respect to a channel width direction.

Semiconductor protection device

To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

Semiconductor integrated circuit and manufacturing method therefore

There is provided a semiconductor integrated circuit device for driving a display element of an organic EL display device, in which an output current is controlled with high accuracy. The semiconductor integrated circuit device includes a field effect MOS transistor capable of obtaining a high accuracy output current and used for an output circuit for driving the display element of the organic EL display device, and further, a fuse trimming element is provided to its gate electrode, so that the device is constructed by the field effect MOS transistor capable of obtaining a more accurate output current. Besides, the field effect MOS transistor has such a structure that even if Vth fluctuates, fluctuation in an output current value is kept low.

Semiconductor integrated circuit device

A thermal head driving integrated circuit capable of preventing the lowering of data transfer speed, and in which the number of bonding pads can be reduced as well as current consumption has a driver circuit in which at least two shift registers are series-arranged in front and rear stages to sequentially transfer print data in a serial signal manner to be read out in a batch mode to drive a plurality of heating resistive elements. A switch circuit is interposed between an output terminal of the front-staged shift register and an input terminal of the rear-staged shift register to selectively connect and disconnect the two shift registers.

Growing community of inventors

Chiba, Japan

Kazutoshi Ishii